Issued Patents 2023
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854894 | Integrated circuit device structures and double-sided electrical testing | Valluri Rao, Patrick Morrow, Doug B. Ingerly, Kimin Jun, Kevin P. O'Brien +3 more | 2023-12-26 |
| 11843052 | Transistor contact area enhancement | Tahir Ghani, Stephen M. Cea | 2023-12-12 |
| 11824107 | Wrap-around contact structures for semiconductor nanowires and nanoribbons | Tahir Ghani, Stephen M. Cea, Biswajeet Guha | 2023-11-21 |
| 11824097 | Contact architecture for capacitance reduction and satisfactory contact resistance | Pratik A. Patel, Ralph T. Troeger, Szuya S. Liao | 2023-11-21 |
| 11798838 | Capacitance reduction for semiconductor devices based on wafer bonding | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Kevin Lin | 2023-10-24 |
| 11798991 | Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly | Aaron D. Lilak, Willy Rachmady, Harold W. Kennel, Tahir Ghani | 2023-10-24 |
| 11742346 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Ehren Mannebach +4 more | 2023-08-29 |
| 11721735 | Thin film transistors having U-shaped features | Gilbert Dewey, Aaron D. Lilak, Van H. Le, Abhishek A. Sharma, Tahir Ghani +6 more | 2023-08-08 |
| 11705518 | Isolation schemes for gate-all-around transistor devices | Stephen M. Cea, Biswajeet Guha, Tahir Ghani, William Hsu | 2023-07-18 |
| 11688780 | Deep source and drain for transistor structures with back-side contact metallization | Tahir Ghani, Stephen M. Cea | 2023-06-27 |
| 11688637 | Wrap-around contact structures for semiconductor fins | — | 2023-06-27 |
| 11664373 | Isolation walls for vertically stacked transistor structures | Aaron D. Lilak, Patrick Morrow, Gilbert Dewey, Willy Rachmady | 2023-05-30 |
| 11664377 | Forksheet transistor architectures | Aaron D. Lilak, Ehren Mannebach, Patrick Morrow, Willy Rachmady | 2023-05-30 |
| 11658221 | Backside contact structures and fabrication for metal on both sides of devices | Patrick Morrow, Aaron D. Lilak, Kimin Jun | 2023-05-23 |
| 11658183 | Metallization structures under a semiconductor device layer | Aaron D. Lilak, Patrick Morrow, Stephen M. Cea | 2023-05-23 |
| 11658072 | Vertically stacked transistors in a fin | Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow | 2023-05-23 |
| 11652107 | Substrate-less FinFET diode architectures with backside metal contact and subfin regions | Nicholas A. Thomson, Ayan Kar, Kalyan C. Kolluru, Nathan Jack, Rui Ma +2 more | 2023-05-16 |
| 11640961 | III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts | Gilbert Dewey, Ravi Pillarisetty, Jack T. Kavalieros, Aaron D. Lilak, Willy Rachmady +6 more | 2023-05-02 |
| 11616060 | Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rami Hourani, Stephanie A. Bojarski +2 more | 2023-03-28 |
| 11616056 | Vertical diode in stacked transistor architecture | Aaron D. Lilak, Patrick Morrow, Anh Phan, Cheng-Ying Huang, Gilbert Dewey +1 more | 2023-03-28 |
| 11616015 | Integrated circuit device with back-side interconnection to deep source/drain semiconductor | Patrick Morrow, Mauro J. Kobrinsky, Mark Bohr, Tahir Ghani | 2023-03-28 |
| 11605556 | Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures | Aaron D. Lilak, Patrick Morrow | 2023-03-14 |
| 11600696 | Sub-fin leakage reduction for template strained materials | Stephen M. Cea, Anupama Bowonder, Juhyung Nam, Willy Rachmady | 2023-03-07 |
| 11573798 | Stacked transistors with different gate lengths in different device strata | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Ehren Mannebach, Cheng-Ying Huang +2 more | 2023-02-07 |
| 11557676 | Device, method and system to provide a stressed channel of a transistor | Stephen M. Cea, Tahir Ghani, Anand S. Murthy | 2023-01-17 |