SC

Stephen M. Cea

IN Intel: 8 patents #233 of 4,378Top 6%
Google: 2 patents #721 of 4,878Top 15%
DP Daedalus Prime: 1 patents #4 of 13Top 35%
Overall (2023): #6,320 of 537,848Top 2%
11
Patents 2023

Issued Patents 2023

Patent #TitleCo-InventorsDate
11843052 Transistor contact area enhancement Rishabh Mehandru, Tahir Ghani 2023-12-12
11824107 Wrap-around contact structures for semiconductor nanowires and nanoribbons Rishabh Mehandru, Tahir Ghani, Biswajeet Guha 2023-11-21
11757026 Nanowire structures having wrap-around contacts Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael Haverty, Sadasivan Shankar 2023-09-12
11705518 Isolation schemes for gate-all-around transistor devices Rishabh Mehandru, Biswajeet Guha, Tahir Ghani, William Hsu 2023-07-18
11688780 Deep source and drain for transistor structures with back-side contact metallization Rishabh Mehandru, Tahir Ghani 2023-06-27
11676965 Strained tunable nanowire structures and process Tahir Ghani, Anand S. Murthy, Biswajeet Guha 2023-06-13
11658183 Metallization structures under a semiconductor device layer Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow 2023-05-23
11600696 Sub-fin leakage reduction for template strained materials Rishabh Mehandru, Anupama Bowonder, Juhyung Nam, Willy Rachmady 2023-03-07
11581406 Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn +1 more 2023-02-14
11557676 Device, method and system to provide a stressed channel of a transistor Rishabh Mehandru, Tahir Ghani, Anand S. Murthy 2023-01-17
11552197 Nanowire structures having non-discrete source and drain regions Annalisa Cappellani, Martin D. Giles, Rafael Rios, Seiyon Kim, Kelin J. Kuhn 2023-01-10