| 11854894 |
Integrated circuit device structures and double-sided electrical testing |
Valluri Rao, Patrick Morrow, Rishabh Mehandru, Doug B. Ingerly, Kevin P. O'Brien +3 more |
2023-12-26 |
| 11784165 |
Monolithic chip stacking using a die with double-sided interconnect layers |
Anup Pancholi |
2023-10-10 |
| 11721649 |
Microelectronic assemblies |
Adel A. Elsherbini, Patrick Morrow, Henning Braunisch, Brennen Mueller, Shawna M. Liff +2 more |
2023-08-08 |
| 11676966 |
Stacked transistors having device strata with different channel widths |
Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz +4 more |
2023-06-13 |
| 11658221 |
Backside contact structures and fabrication for metal on both sides of devices |
Patrick Morrow, Rishabh Mehandru, Aaron D. Lilak |
2023-05-23 |
| 11640961 |
III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts |
Gilbert Dewey, Ravi Pillarisetty, Jack T. Kavalieros, Aaron D. Lilak, Willy Rachmady +6 more |
2023-05-02 |
| 11605565 |
Three dimensional integrated circuits with stacked transistors |
Cheng-Ying Huang, Willy Rachmady, Gilbert Dewey, Aaron D. Lilak, Brennen Mueller +5 more |
2023-03-14 |
| 11594524 |
Fabrication and use of through silicon vias on double sided interconnect device |
Brennen Mueller, Patrick Morrow, Paul B. Fischer, Daniel Pantuso |
2023-02-28 |
| 11594452 |
Techniques for revealing a backside of an integrated circuit device, and associated configurations |
Il-Seok Son, Colin T. Carver, Paul B. Fischer, Patrick Morrow |
2023-02-28 |
| 11569238 |
Vertical memory cells |
Aaron D. Lilak, Willy Rachmady, Gilbert Dewey, Hui Jae Yoo, Patrick Morrow +5 more |
2023-01-31 |
| 11552104 |
Stacked transistors with dielectric between channels of different device strata |
Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru, Ehren Mannebach +3 more |
2023-01-10 |