EM

Ehren Mannebach

IN Intel: 17 patents #72 of 4,378Top 2%
Overall (2023): #2,890 of 537,848Top 1%
17
Patents 2023

Issued Patents 2023

Patent #TitleCo-InventorsDate
11830933 Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Patrick Morrow +2 more 2023-11-28
11798838 Capacitance reduction for semiconductor devices based on wafer bonding Aaron D. Lilak, Rishabh Mehandru, Hui Jae Yoo, Patrick Morrow, Kevin Lin 2023-10-24
11769814 Device including air gapping of gate spacers and other dielectrics and process for providing such Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Kevin Lin, Tristan A. Tronic 2023-09-26
11764263 Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches Anh Phan, Aaron D. Lilak, Willy Rachmady, Gilbert Dewey, Cheng-Ying Huang +3 more 2023-09-19
11764104 Forming an oxide volume within a fin Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Patrick Morrow +3 more 2023-09-19
11742346 Interconnect techniques for electrically connecting source/drain regions of stacked transistors Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Rishabh Mehandru +4 more 2023-08-29
11676966 Stacked transistors having device strata with different channel widths Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz +4 more 2023-06-13
11672133 Vertically stacked memory elements with air gap Aaron D. Lilak, Patrick Morrow, Hui Jae Yoo, Sean T. Ma, Scott B. Clendenning +2 more 2023-06-06
11664377 Forksheet transistor architectures Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow, Willy Rachmady 2023-05-30
11646352 Stacked source-drain-gate connection and process for forming such Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +2 more 2023-05-09
11616060 Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rami Hourani, Stephanie A. Bojarski +2 more 2023-03-28
11605565 Three dimensional integrated circuits with stacked transistors Cheng-Ying Huang, Willy Rachmady, Gilbert Dewey, Aaron D. Lilak, Kimin Jun +5 more 2023-03-14
11594533 Stacked trigate transistors with dielectric isolation between first and second semiconductor fins Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron D. Lilak, Patrick Morrow +2 more 2023-02-28
11594485 Local interconnect with air gap Kevin Lin, Scott B. Clendenning, Tristan A. Tronic, Urusa Alaan 2023-02-28
11573798 Stacked transistors with different gate lengths in different device strata Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru, Cheng-Ying Huang +2 more 2023-02-07
11569238 Vertical memory cells Aaron D. Lilak, Willy Rachmady, Gilbert Dewey, Kimin Jun, Hui Jae Yoo +5 more 2023-01-31
11552104 Stacked transistors with dielectric between channels of different device strata Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru, Cheng-Ying Huang +3 more 2023-01-10