Issued Patents 2023
Showing 1–25 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854902 | Integrated circuits with buried interconnect conductors | Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang | 2023-12-26 |
| 11855138 | Semiconductor device structure | Jung-Chien Cheng, Kuo-Cheng Chiang, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng | 2023-12-26 |
| 11855096 | Uniform gate width for nanostructure devices | Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin +3 more | 2023-12-26 |
| 11855079 | Integrated circuit with backside trench for metal gate definition | Kuo-Cheng Chiang, Jung-Chien Cheng, Guan-Lin Chen, Chih-Hao Wang | 2023-12-26 |
| 11855078 | Semiconductor device structure including forksheet transistors and methods of forming the same | Guan-Lin Chen, Kuo-Cheng Chiang, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng | 2023-12-26 |
| 11854908 | Multi-gate device and related methods | Kuan-Ting Pan, Huan-Chieh Su, Zhi-Chang Lin, Yi-Ruei Jhan, Kuo-Cheng Chiang +1 more | 2023-12-26 |
| 11848329 | Semiconductor structure with self-aligned backside power rail | Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang | 2023-12-19 |
| 11842965 | Backside power rail structure and methods of forming same | Kuo-Cheng Chiang, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang | 2023-12-12 |
| 11837504 | Self-aligned structure for semiconductor devices | Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng, Kuan-Ting Pan | 2023-12-05 |
| 11824058 | Method of forming semiconductor device | Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang | 2023-11-21 |
| 11817504 | Isolation structures and methods of forming the same in field-effect transistors | Kuo-Cheng Chiang, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng | 2023-11-14 |
| 11804489 | Semiconductor device and manufacturing method thereof | Kuo-Cheng Ching, Chih-Hao Wang, Chih-Liang Chen | 2023-10-31 |
| 11799019 | Gate isolation feature and manufacturing method thereof | Kuan-Ting Pan, Huan-Chieh Su, Jia-Chuan You, Kuo-Cheng Chiang, Yi-Ruei Jhan +2 more | 2023-10-24 |
| 11798944 | Integration of silicon channel nanostructures and silicon-germanium channel nanostructures | Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng, Guan-Lin Chen | 2023-10-24 |
| 11764286 | Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers | Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng | 2023-09-19 |
| 11756958 | Semiconductor device structure and methods of forming the same | Jia-Chuan You, Kuo-Cheng Chiang, Chih-Hao Wang | 2023-09-12 |
| 11742415 | Fin-like field effect transistor patterning methods for achieving fin width uniformity | Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang | 2023-08-29 |
| 11742428 | Formation method of semiconductor device with isolation structure | Kuo-Cheng Chiang, Huan-Chieh Su, Kuan-Ting Pan, Chih-Hao Wang | 2023-08-29 |
| 11742280 | Integrated circuits with backside power rails | Chih-Chao Chou, Kuo-Cheng Chiang, Wen-Ting Lan, Chih-Hao Wang | 2023-08-29 |
| 11735649 | Method for forming fin field effect transistor (FinFET) with a liner layer | Kuo-Cheng Ching, Kuan-Ting Pan, Chih-Hao Wang | 2023-08-22 |
| 11735591 | Semiconductor devices with dielectric fins and method for forming the same | Kuan-Ting Pan, Chih-Hao Wang, Jia-Chuan You, Kuo-Cheng Chiang | 2023-08-22 |
| 11710737 | Hybrid semiconductor device | Jung-Chien Cheng, Kuo-Cheng Chiang, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng | 2023-07-25 |
| 11699729 | Semiconductor devices and methods | Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang | 2023-07-11 |
| 11682697 | Fin recess last process for FinFET fabrication | Kuo-Cheng Chiang, Guan-Lin Chen | 2023-06-20 |
| 11676864 | Semiconductor device structure and methods of forming the same | Kuan-Ting Pan, Kuo-Cheng Chiang, Shang-Wen Chang, Chih-Hao Wang | 2023-06-13 |