Issued Patents 2023
Showing 1–25 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11855078 | Semiconductor device structure including forksheet transistors and methods of forming the same | Guan-Lin Chen, Shi Ning Ju, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng | 2023-12-26 |
| 11854908 | Multi-gate device and related methods | Kuan-Ting Pan, Huan-Chieh Su, Zhi-Chang Lin, Shi Ning Ju, Yi-Ruei Jhan +1 more | 2023-12-26 |
| 11855216 | Inner spacers for gate-all-around transistors | Zhi-Chang Lin, Shih-Cheng Chen, Chih-Hao Wang, Pei-Hsun Wang, Lo-Heng Chang +1 more | 2023-12-26 |
| 11855096 | Uniform gate width for nanostructure devices | Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Zhi-Chang Lin, Jung-Hung Chang +3 more | 2023-12-26 |
| 11854902 | Integrated circuits with buried interconnect conductors | Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2023-12-26 |
| 11855138 | Semiconductor device structure | Jung-Chien Cheng, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng | 2023-12-26 |
| 11854905 | Silicon and silicon germanium nanowire formation | Jin-Aun Ng, Carlos H. Diaz, Jean-Pierre Colinge | 2023-12-26 |
| 11855079 | Integrated circuit with backside trench for metal gate definition | Jung-Chien Cheng, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang | 2023-12-26 |
| 11848329 | Semiconductor structure with self-aligned backside power rail | Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2023-12-19 |
| 11848368 | Transistors with different threshold voltages | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Chih-Hao Wang | 2023-12-19 |
| 11842965 | Backside power rail structure and methods of forming same | Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang | 2023-12-12 |
| 11837504 | Self-aligned structure for semiconductor devices | Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng, Kuan-Ting Pan | 2023-12-05 |
| 11830924 | Nanosheet device with dipole dielectric layer and methods of forming the same | Chung-Wei Hsu, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu, Chih-Hao Wang | 2023-11-28 |
| 11817504 | Isolation structures and methods of forming the same in field-effect transistors | Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng | 2023-11-14 |
| 11799019 | Gate isolation feature and manufacturing method thereof | Kuan-Ting Pan, Huan-Chieh Su, Jia-Chuan You, Shi Ning Ju, Yi-Ruei Jhan +2 more | 2023-10-24 |
| 11798944 | Integration of silicon channel nanostructures and silicon-germanium channel nanostructures | Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng, Guan-Lin Chen | 2023-10-24 |
| 11791218 | Dipole patterning for CMOS devices | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Chih-Hao Wang | 2023-10-17 |
| 11791401 | Multi-gate device and related methods | Shih-Cheng Chen, Zhi-Chang Lin | 2023-10-17 |
| 11784241 | Devices including gate spacer with gap or void and methods of forming the same | Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung | 2023-10-10 |
| 11756958 | Semiconductor device structure and methods of forming the same | Jia-Chuan You, Shi Ning Ju, Chih-Hao Wang | 2023-09-12 |
| 11756995 | Method of forming a semiconductor device structure having an isolation layer to isolate a conductive feature and a gate electrode layer | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2023-09-12 |
| 11757021 | Semiconductor devices with fin-top hard mask and methods for fabrication thereof | Yi-Ruei Jhan, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang | 2023-09-12 |
| 11742428 | Formation method of semiconductor device with isolation structure | Huan-Chieh Su, Kuan-Ting Pan, Shi Ning Ju, Chih-Hao Wang | 2023-08-29 |
| 11742280 | Integrated circuits with backside power rails | Chih-Chao Chou, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang | 2023-08-29 |
| 11735482 | Semiconductor device structure and methods of forming the same | Kuan-Ting Pan, Shang-Wen Chang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang | 2023-08-22 |