Issued Patents 2023
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11848368 | Transistors with different threshold voltages | Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang | 2023-12-19 |
| 11830924 | Nanosheet device with dipole dielectric layer and methods of forming the same | Chung-Wei Hsu, Kuo-Cheng Chiang, Lung-Kun Chu, Jia-Ni Yu, Chih-Hao Wang | 2023-11-28 |
| 11791218 | Dipole patterning for CMOS devices | Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang | 2023-10-17 |
| 11756995 | Method of forming a semiconductor device structure having an isolation layer to isolate a conductive feature and a gate electrode layer | Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuan-Lun Cheng, Kuo-Cheng Chiang +1 more | 2023-09-12 |
| 11728401 | Semiconductor structures and methods thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2023-08-15 |
| 11710667 | Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same | Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Ching-Wei Tsai +3 more | 2023-07-25 |
| 11676866 | Semiconductor arrangement and method of manufacture | Kuo-Cheng Ching, Lung-Kun Chu, Chung-Wei Hsu | 2023-06-13 |
| 11670692 | Gate-all-around devices having self-aligned capping between channel and backside power rail | Chung-Wei Hsu, Lung-Kun Chu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng +1 more | 2023-06-06 |
| 11670723 | Silicon channel tempering | Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng +1 more | 2023-06-06 |
| 11658837 | Multicast packet replication method | Kuo-Cheng Lu, Yung-Chang Lin | 2023-05-23 |
| 11637195 | Metal gate patterning process including dielectric Fin formation | Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang | 2023-04-25 |
| 11626485 | Field effect transistor and method | Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng +1 more | 2023-04-11 |
| 11626327 | Methods of fabricating semiconductor devices with mixed threshold voltages boundary isolation of multiple gates and structures formed thereby | Kuo-Cheng Chiang, Chung-Wei Hsu, Lung-Kun Chu, Jia-Ni Yu, Chih-Hao Wang | 2023-04-11 |
| 11615962 | Semiconductor structures and methods thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2023-03-28 |
| 11600533 | Semiconductor device fabrication methods and structures thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2023-03-07 |
| 11594614 | P-metal gate first gate replacement process for multigate devices | Jia-Ni Yu, Kuo-Cheng Chiang, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang | 2023-02-28 |
| 11563109 | Semiconductor device structure and method for forming the same | Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Chun-Fu Lu, Kuo-Cheng Chiang +2 more | 2023-01-24 |