Issued Patents 2023
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11855224 | Leakage prevention structure and method | Yi-Bo Liao, Sai-Hooi Yeong, Hou-Yu Chen, Yu-Xuan Huang, Kuan-Lun Cheng | 2023-12-26 |
| 11855090 | High performance MOSFETs having varying channel structures | Tetsu Ohtou, Jiun-Jia Huang, Kuan-Lun Cheng, Chi-Hsing Hsu | 2023-12-26 |
| 11854940 | Semiconductor device having self-aligned interconnect structure and method of making | Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang +1 more | 2023-12-26 |
| 11837535 | Semiconductor devices including decoupling capacitors | Yu-Xuan Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chung-Hui Chen | 2023-12-05 |
| 11824058 | Method of forming semiconductor device | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2023-11-21 |
| 11810917 | Self-aligned etch in semiconductor devices | Yi-Hsun Chiu, Yu-Xuan Huang, Cheng-Chi Chuang, Shang-Wen Chang | 2023-11-07 |
| 11784235 | Negative capacitance transistor having a multilayer ferroelectric structure or a ferroelectric layer with a gradient doping profile | Chi-Hsing Hsu, Sai-Hooi Yeong, Chih-Yu Chang, Kuan-Lun Cheng | 2023-10-10 |
| 11784241 | Devices including gate spacer with gap or void and methods of forming the same | Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung | 2023-10-10 |
| 11784233 | Integrated circuit structure with backside via rail | Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Shang-Wen Chang +3 more | 2023-10-10 |
| 11764213 | Amphi-FET structure, method of making and method of designing | Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang +1 more | 2023-09-19 |
| 11764154 | Power rail and signal line arrangement in integrated circuits having stacked transistors | Chih-Liang Chen, Guo-Huei Wu, Shang-Wen Chang, Li-Chun Tien | 2023-09-19 |
| 11757042 | Semiconductor device and method | Yi-Bo Liao, Yu-Xuan Huang, Pei-Yu Wang, Cheng-Ting Chung, Hou-Yu Chen | 2023-09-12 |
| 11756959 | Structure and method of integrated circuit having decouple capacitance | Yu-Xuan Huang, Kuan-Lun Cheng, Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu | 2023-09-12 |
| 11735482 | Semiconductor device structure and methods of forming the same | Kuan-Ting Pan, Kuo-Cheng Chiang, Shang-Wen Chang, Kuan-Lun Cheng, Chih-Hao Wang | 2023-08-22 |
| 11735594 | Integrated circuit structure and method with hybrid orientation for FinFET | Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Kuan-Lun Cheng, Chih-Hao Wang +1 more | 2023-08-22 |
| 11735587 | Backside PN junction diode | Yu-Xuan Huang, Jam-Wem Lee, Kuo-Ji Chen, Kuan-Lun Cheng | 2023-08-22 |
| 11715781 | Semiconductor devices with improved capacitors | Wang-Chun Huang, Kuan-Lun Cheng, Chih-Hao Wang | 2023-08-01 |
| 11710667 | Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same | Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Chih-Hao Wang +3 more | 2023-07-25 |
| 11705488 | Nano-sheet-based devices with asymmetric source and drain configurations | Cheng-Ting Chung, Yu-Xuan Huang, Yi-Bo Liao, Kuan-Lun Cheng | 2023-07-18 |
| 11699733 | Semiconductor devices | Cheng-Ting Chung, Kuan-Lun Cheng | 2023-07-11 |
| 11676819 | Method for metal gate cut and structure thereof | Pei-Yu Wang, Zhi-Chang Lin, Kuan-Lun Cheng | 2023-06-13 |
| 11664374 | Backside interconnect structures for semiconductor devices and methods of forming the same | Cheng-Ting Chung, Hou-Yu Chen | 2023-05-30 |
| 11664454 | Method for forming semiconductor device structure | Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2023-05-30 |
| 11664451 | Method and device for boosting performance of FinFETs via strained spacer | Kai-Chieh Yang, Li-Yang Chuang, Pei-Yu Wang, Wei Ju Lee, Kuan-Lun Cheng | 2023-05-30 |
| 11658119 | Backside signal interconnection | Yu-Xuan Huang, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng, Wei-Cheng Lin +6 more | 2023-05-23 |