Issued Patents 2023
Showing 1–25 of 144 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854902 | Integrated circuits with buried interconnect conductors | Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng | 2023-12-26 |
| 11855096 | Uniform gate width for nanostructure devices | Jui-Chien Huang, Shih-Cheng Chen, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang +3 more | 2023-12-26 |
| 11854866 | Enlarging contact area and process window for a contact via | Li-Zhen Yu, Cheng-Chi Chuang, Yu-Ming Lin, Lin-Yu Huang | 2023-12-26 |
| 11855084 | Integrated circuits with FinFET gate structures | Kuo-Cheng Ching, Huan-Chieh Su, Zhi-Chang Lin | 2023-12-26 |
| 11855205 | Semiconductor device with negative capacitance structure | Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi On Chui | 2023-12-26 |
| 11855079 | Integrated circuit with backside trench for metal gate definition | Kuo-Cheng Chiang, Jung-Chien Cheng, Shi Ning Ju, Guan-Lin Chen | 2023-12-26 |
| 11855216 | Inner spacers for gate-all-around transistors | Kuo-Cheng Chiang, Zhi-Chang Lin, Shih-Cheng Chen, Pei-Hsun Wang, Lo-Heng Chang +1 more | 2023-12-26 |
| 11855144 | Source/drain metal contact and formation thereof | Shih-Chuan Chiu, Chia-Hao Chang, Jia-Chuan You, Tien-Lu Lin, Yu-Ming Lin | 2023-12-26 |
| 11855138 | Semiconductor device structure | Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng | 2023-12-26 |
| 11855178 | Semiconductor devices having air-gap | Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Chao Chou, Chia-Hao Chang | 2023-12-26 |
| 11855078 | Semiconductor device structure including forksheet transistors and methods of forming the same | Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Jung-Chien Cheng, Kuan-Lun Cheng | 2023-12-26 |
| 11855082 | Integrated circuits with FinFET gate structures | Kuo-Cheng Ching, Huan-Chieh Su, Zhi-Chang Lin | 2023-12-26 |
| 11854908 | Multi-gate device and related methods | Kuan-Ting Pan, Huan-Chieh Su, Zhi-Chang Lin, Shi Ning Ju, Yi-Ruei Jhan +1 more | 2023-12-26 |
| 11848326 | Integrated circuits with gate cut features | Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Kuo-Cheng Ching | 2023-12-19 |
| 11848329 | Semiconductor structure with self-aligned backside power rail | Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng | 2023-12-19 |
| 11848368 | Transistors with different threshold voltages | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang | 2023-12-19 |
| 11848372 | Method and structure for reducing source/drain contact resistance at wafer backside | Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Kuan-Lun Cheng | 2023-12-19 |
| 11842965 | Backside power rail structure and methods of forming same | Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan | 2023-12-12 |
| 11837506 | FinFET devices and methods of forming the same | Jui-Chien Huang, Kuo-Cheng Ching, Chun-Hsiung Lin, Pei-Hsun Wang | 2023-12-05 |
| 11837504 | Self-aligned structure for semiconductor devices | Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Kuan-Ting Pan | 2023-12-05 |
| 11830924 | Nanosheet device with dipole dielectric layer and methods of forming the same | Chung-Wei Hsu, Kuo-Cheng Chiang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu | 2023-11-28 |
| 11830769 | Semiconductor device with air gaps and method of fabrication thereof | Chia-Hao Chang, Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng | 2023-11-28 |
| 11824058 | Method of forming semiconductor device | Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng | 2023-11-21 |
| 11824101 | High aspect ratio gate structure formation | Sai-Hooi Yeong, Chi On Chui, Kai-Hsuan Lee, Kuan-Lun Cheng | 2023-11-21 |
| 11817491 | Semiconductor device having an air gap along a gate spacer | Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin | 2023-11-14 |