Issued Patents 2023
Showing 26–50 of 144 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11817491 | Semiconductor device having an air gap along a gate spacer | Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin | 2023-11-14 |
| 11804486 | Backside power rail and methods of forming the same | Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Shih-Chuan Chiu, Cheng-Chi Chuang +1 more | 2023-10-31 |
| 11804489 | Semiconductor device and manufacturing method thereof | Kuo-Cheng Ching, Chih-Liang Chen, Shi Ning Ju | 2023-10-31 |
| 11798944 | Integration of silicon channel nanostructures and silicon-germanium channel nanostructures | Shi Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng, Guan-Lin Chen | 2023-10-24 |
| 11799019 | Gate isolation feature and manufacturing method thereof | Kuan-Ting Pan, Huan-Chieh Su, Jia-Chuan You, Shi Ning Ju, Kuo-Cheng Chiang +2 more | 2023-10-24 |
| 11798884 | Contact via formation | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng | 2023-10-24 |
| 11791218 | Dipole patterning for CMOS devices | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang | 2023-10-17 |
| 11784228 | Process and structure for source/drain contacts | Meng-Huan Jao, Lin-Yu Huang, Sheng-Tsung Wang, Huan-Chieh Su, Cheng-Chi Chuang | 2023-10-10 |
| 11784233 | Integrated circuit structure with backside via rail | Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Shang-Wen Chang +3 more | 2023-10-10 |
| 11777033 | Transistors having vertical nanostructures | Pei-Hsun Wang, Chun-Hsiung Lin, Cheng-Ting Chung | 2023-10-03 |
| 11776854 | Semiconductor structure with hybrid nanostructures | Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Chao Chou | 2023-10-03 |
| 11777003 | Semiconductor structure with wraparound backside amorphous layer | Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen +3 more | 2023-10-03 |
| 11777009 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Jean-Pierre Colinge, Chun-Hsiung Lin +2 more | 2023-10-03 |
| 11769696 | Method for fabricating a semiconductor device | Chun-Yuan Chen, Li-Zhen Yu, Huan-Chieh Su, Lo-Heng Chang, Cheng-Chi Chuang | 2023-09-26 |
| 11764203 | Integrated hybrid standard cell structure with gate-all-around device | Shang-Wen Chang, Min Cao | 2023-09-19 |
| 11764286 | Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng | 2023-09-19 |
| 11764065 | Methods of forming silicide contact in field-effect transistors | Chun-Hsiung Lin, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang | 2023-09-19 |
| 11764292 | Negative-capacitance field effect transistor | Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi On Chui | 2023-09-19 |
| 11764281 | Gate air spacer for fin-like field effect transistor | Chien Ning Yao, Bo-Feng Young, Sai-Hooi Yeong, Kuan-Lun Cheng | 2023-09-19 |
| 11756995 | Method of forming a semiconductor device structure having an isolation layer to isolate a conductive feature and a gate electrode layer | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2023-09-12 |
| 11756958 | Semiconductor device structure and methods of forming the same | Jia-Chuan You, Shi Ning Ju, Kuo-Cheng Chiang | 2023-09-12 |
| 11757021 | Semiconductor devices with fin-top hard mask and methods for fabrication thereof | Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng | 2023-09-12 |
| 11749728 | Semiconductor device and manufacturing method thereof | Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin | 2023-09-05 |
| 11749725 | Methods of forming source/drain contacts in field-effect transistors | Sheng-Tsung Wang, Chia-Hao Chang, Yu-Ming Lin | 2023-09-05 |
| 11742280 | Integrated circuits with backside power rails | Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan | 2023-08-29 |