RM

Robert Alan May

IN Intel: 11 patents #133 of 4,378Top 4%
TR Tahoe Research: 1 patents #11 of 144Top 8%
Overall (2023): #5,432 of 537,848Top 2%
12
Patents 2023

Issued Patents 2023

Patent #TitleCo-InventorsDate
11854834 Integrated circuit package supports Kristof Darmawikarta, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov 2023-12-26
11817390 Microelectronic component having molded regions with through-mold vias Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba +1 more 2023-11-14
11784128 Die interconnect substrate, an electrical device and a method for forming a die interconnect substrate Kristof Darmawikarta, Sri Ranga Sai Boyapati 2023-10-10
11764158 Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same Amruthavalli Pallavi Alur, Sri Ranga Sai Boyapati, Islam A. Salama, Robert L. Sankman 2023-09-19
11735531 Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Javier Soto Gonzalez, Kwangmo Chris Lim 2023-08-22
11721631 Via structures having tapered profiles for embedded interconnect bridge substrates Jeremy Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh +2 more 2023-08-08
11699648 Electromigration resistant and profile consistent contact arrays Srinivas V. Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas HEATON +3 more 2023-07-11
11688692 Embedded multi-die interconnect bridge having a substrate with conductive pathways and a molded material region with through-mold vias Praneeth Akkinepally, Frank Truong, Jason M. Gamba 2023-06-27
11658122 EMIB patch on glass laminate substrate Robert L. Sankman 2023-05-23
11640942 Microelectronic component having molded regions with through-mold vias Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba +1 more 2023-05-02
11574874 Package architecture utilizing photoimageable dielectric (PID) for reduced bump pitch Sri Ranga Sai Boyapati, Kristof Darmawikarta, Hiroki Tanaka, Srinivas V. Pietambaram, Frank Truong +4 more 2023-02-07
11552010 Dielectric for high density substrate interconnects Andrew J. Brown, Sri Ranga Sai Boyapati, Kristof Darmawikarta 2023-01-10