Issued Patents 2021
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11205615 | Semiconductor device and method of manufacture | Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Szu-Wei Lu, Ying-Ching Shih | 2021-12-21 |
| 11205579 | Molding wafer chamber | Chin-Chuan Chang, Jui-Pin Hung, Szu-Wei Lu, Shin-Puu Jeng, Chen-Hua Yu | 2021-12-21 |
| 11201135 | Three dimensional integrated circuits stacking approach | Shang-Yun Hou | 2021-12-14 |
| 11183473 | Integrated circuit structure having dies with connectors of different sizes | Shin-Puu Jeng, Chen-Hua Yu | 2021-11-23 |
| 11164829 | Method of forming contact holes in a fan out package | Feng-Cheng Hsu, Szu-Wei Lu | 2021-11-02 |
| 11164852 | Method of forming package structure | Po-Hao Tsai | 2021-11-02 |
| 11158587 | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices | Po-Hao Tsai, Jui-Pin Hung | 2021-10-26 |
| 11158588 | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices | Po-Hao Tsai, Jui-Pin Hung | 2021-10-26 |
| 11152316 | Method of forming contact holes in a fan out package | Feng-Cheng Hsu, Szu-Wei Lu | 2021-10-19 |
| 11139285 | Semiconductor package | Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Ying-Ching Shih, Szu-Wei Lu | 2021-10-05 |
| 11133286 | Chip packages and methods of manufacture thereof | Chih-Wei Wu, Szu-Wei Lu, Ying-Ching Shih | 2021-09-28 |
| 11121118 | Integrated circuit stacking approach | Shang-Yun Hou | 2021-09-14 |
| 11114405 | Semiconductor package structure with twinned copper | Jung-Hua Chang, Po-Hao Tsai | 2021-09-07 |
| 11107798 | Semiconductor packages and methods of forming the same | Chen-Hua Yu, Po-Hao Tsai | 2021-08-31 |
| 11101252 | Package-on-package structure and manufacturing method thereof | Shih-Ting Lin, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu | 2021-08-24 |
| 11094639 | Semiconductor package | Po-Hao Tsai, Ying-Ching Shih, Szu-Wei Lu | 2021-08-17 |
| 11081475 | Integrated circuit structure and method for reducing polymer layer delamination | Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin | 2021-08-03 |
| 11075168 | InFO-POP structures with TIVs having cavities | Chen-Hua Yu, Po-Hao Tsai | 2021-07-27 |
| 11075133 | Underfill structure for semiconductor packages and methods of forming the same | Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Long Hua Lee +1 more | 2021-07-27 |
| 11069673 | Semiconductor package and manufacturing method thereof | Li-Hui Cheng, Po-Hao Tsai | 2021-07-20 |
| 11069653 | Methods and structures for packaging semiconductor dies | Yi-Chao Mao | 2021-07-20 |
| 11062987 | Semiconductor device | Chi-Hsi Wu, Chen-Hua Yu, Po-Hao Tsai | 2021-07-13 |
| 11056436 | Integrated fan-out structure with rugged interconnect | Shih-Ting Lin, Szu-Wei Lu, Chen-Hua Yu | 2021-07-06 |
| 11056471 | Semiconductor device and method of manufacture | Po-Hao Tsai, Li-Hui Cheng, Porter Chen | 2021-07-06 |
| 11037854 | Thermal dissipation through seal rings in 3DIC structure | Shih-Yi Syu | 2021-06-15 |