Issued Patents 2021
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11037861 | Interconnect structure for package-on-package devices | Jui-Pin Hung, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh +1 more | 2021-06-15 |
| 11018106 | Semiconductor device including solder bracing material with a rough surface, and manufacturing method thereof | Feng-Cheng Hsu | 2021-05-25 |
| 10964594 | Methods of packaging semiconductor devices including placing semiconductor devices into die caves | Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung | 2021-03-30 |
| 10964673 | Semiconductor device and manufacturing method of the same | Ying-Ching Shih, Pu Wang, Chen-Hua Yu | 2021-03-30 |
| 10957616 | Package structure and method | Szu-Wei Lu, Chen-Hua Yu | 2021-03-23 |
| 10943873 | Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same | Chen-Hua Yu, Szu-Wei Lu, Yen-Yao Chi | 2021-03-09 |
| 10923431 | Method for forming a 3D IC architecture including forming a first die on a first side of a first interconnect structure and a second die in an opening formed in a second side | Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jiun-Ren Lai, Yung-Chi Lin | 2021-02-16 |
| 10916450 | Package of integrated circuits having a light-to-heat-conversion coating material | Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Szu-Wei Lu, Ying-Ching Shih | 2021-02-09 |
| 10916488 | Semiconductor package having thermal conductive pattern surrounding the semiconductor die | Szu-Wei Lu | 2021-02-09 |
| 10910267 | Alignment marks in substrate having through-substrate via (TSV) | Hsin Chang, Fang Wen Tsai, Wen-Chih Chiou, Shin-Puu Jeng | 2021-02-02 |