Issued Patents 2018
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163851 | Tri-layer CoWoS structure | Chen-Hua Yu, Yun-Han Lee | 2018-12-25 |
| 10163856 | Stacked integrated circuit structure and method of forming | Wei-Ming Chen, Hsien-Pin Hu, Wen-Hsin Wei | 2018-12-25 |
| 10163853 | Formation method of chip package | Wen-Hsin Wei, Chi-Hsi Wu, Chen-Hua Yu, Hsien-Pin Hu, Wei-Ming Chen | 2018-12-25 |
| 10153205 | Package with metal-insulator-metal capacitor and method of manufacturing the same | Chen-Hua Yu, Wen-Chih Chiou, Jui-Pin Hung, Der-Chyang Yeh, Chiung-Han Yeh | 2018-12-11 |
| 10153222 | Package structures and methods of forming the same | Chen-Hua Yu, Hsien-Pin Hu, Jing-Cheng Lin, Szu-Wei Lu, Wen-Hsin Wei +2 more | 2018-12-11 |
| 10153338 | Method of manufacturing a capacitor | Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Wen-Chih Chiou +1 more | 2018-12-11 |
| 10090213 | Interposer test structures and methods | Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu +1 more | 2018-10-02 |
| 10056347 | Bump structure for yield improvement | Tzu-Wei Chiu, Tzu-Yu Wang, Shin-Puu Jeng, Hsien-Wei Chen, Hung-An Teng +1 more | 2018-08-21 |
| 9984981 | Packages with interposers and methods for forming the same | Sao-Ling Chiu, Kuo-Ching Hsu, Wei-Cheng Wu, Ping-Kang Huang, Shin-Puu Jeng +1 more | 2018-05-29 |
| 9978637 | Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs) | Tzuan-Horng Liu, Shih-Wen Huang, Chung-Yu Lu, Hsien-Pin Hu, Shin-Puu Jeng | 2018-05-22 |
| 9953948 | Pillar design for conductive bump | Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Jing-Cheng Lin, Shin-Puu Jeng | 2018-04-24 |
| 9859235 | Underbump metallization structure | Yu-Wen Liu, Hao-Yi Tsai, Hsien-Wei Chen, Shin-Puu Jeng, Ying-Ju Chen +2 more | 2018-01-02 |