Issued Patents 2018
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163875 | Method for forming chip package structure with adhesive layer | Li-Hui Cheng, Jing-Cheng Lin, Yi-Hang Lin | 2018-12-25 |
| 10163872 | Semiconductor packages and methods of forming the same | Chen-Hua Yu, Jing-Cheng Lin | 2018-12-25 |
| 10163848 | Semiconductor package | Jing-Cheng Lin, Li-Hui Cheng, Chih-Chien Pan | 2018-12-25 |
| 10163813 | Chip package structure including redistribution structure and conductive shielding film | Jing-Cheng Lin | 2018-12-25 |
| 10157888 | Integrated fan-out packages and methods of forming the same | Jing-Cheng Lin, Tsung-Fu Tsai, Chen-Hua Yu, Shih-Ting Lin, Szu-Wei Lu +2 more | 2018-12-18 |
| 10141253 | Semiconductor device and method | Jing-Cheng Lin, Chi-Hsi Wu, Chen-Hua Yu | 2018-11-27 |
| 10134719 | Semiconductor package and manufacturing method thereof | Li-Hui Cheng, Jing-Cheng Lin | 2018-11-20 |
| 10128226 | Mechanisms for forming package structure | Jing-Cheng Lin | 2018-11-13 |
| 10115675 | Packaged semiconductor device and method of fabricating a packaged semiconductor device | Jing-Cheng Lin, Li-Hui Cheng | 2018-10-30 |
| 10109573 | Packaged semiconductor devices and packaging devices and methods | Jing-Cheng Lin | 2018-10-23 |
| 10103125 | Chip package structure and method for forming the same | Chen-Hua Yu, Jing-Cheng Lin, An-Jhih Su | 2018-10-16 |
| 10103132 | Semiconductor device and method of manufactures | Jing-Cheng Lin, Li-Hui Cheng | 2018-10-16 |
| 10090253 | Semiconductor package | Jing-Cheng Lin, Ying-Ching Shih, Szu-Wei Lu | 2018-10-02 |
| 10083946 | Integrated fan-out structure with guiding trenches in buffer layer | Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin | 2018-09-25 |
| 10062662 | Integrated fan-out package structures with recesses in molding compound | Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin | 2018-08-28 |
| 10049989 | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices | Jui-Pin Hung, Jing-Cheng Lin | 2018-08-14 |
| 10008485 | Semiconductor device and method of manufacture | Jing-Cheng Lin, Li-Hui Cheng, Porter Chen | 2018-06-26 |
| 9953949 | Through package via (TPV) | Jing-Cheng Lin | 2018-04-24 |
| 9953955 | Integrated fan-out package structures with recesses in molding compound | Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin | 2018-04-24 |
| 9953948 | Pillar design for conductive bump | Cheng-Chieh Hsieh, Cheng-Lin Huang, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng | 2018-04-24 |
| 9929108 | Backside redistribution layer (RDL) structure | Jing-Cheng Lin | 2018-03-27 |
| 9929128 | Chip package structure with adhesive layer | Li-Hui Cheng, Jing-Cheng Lin, Yi-Hang Lin | 2018-03-27 |
| 9922903 | Interconnect structure for package-on-package devices and a method of fabricating | Jui-Pin Hung, Jing-Cheng Lin, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh +1 more | 2018-03-20 |