Issued Patents 2016
Showing 25 most recent of 280 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530669 | Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-12-27 |
| 9530772 | Methods of manufacturing devices including gates with multiple lengths | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-12-27 |
| 9530843 | FinFET having an epitaxially grown semiconductor on the fin in the channel region | Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek, Davood Shahrjerdi | 2016-12-27 |
| 9530701 | Method of forming semiconductor fins on SOI substrate | Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang | 2016-12-27 |
| 9530698 | Method and structure for forming FinFET CMOS with dual doped STI regions | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2016-12-27 |
| 9530775 | Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices | Xiuyu Cai, Ruilong Xie, Ali Khakifirooz | 2016-12-27 |
| 9525064 | Channel-last replacement metal-gate vertical field effect transistor | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-12-20 |
| 9525147 | Fringing field assisted dielectrophoresis assembly of carbon nanotubes | Qing Cao, Shu-Jen Han, Zhengwen Li, Fei Liu | 2016-12-20 |
| 9524969 | Integrated circuit having strained fins on bulk substrate | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-12-20 |
| 9520469 | Fabrication of fin structures having high germanium content | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-12-13 |
| 9520392 | Semiconductor device including finFET and fin varactor | Junli Wang, Ruilong Xie, Tenko Yamashita | 2016-12-13 |
| 9520397 | Abrupt source/drain junction formation using a diffusion facilitation layer | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-12-13 |
| 9520328 | Type III-V and type IV semiconductor device formation | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-12-13 |
| 9520363 | Forming CMOSFET structures with different contact liners | Zuoguang Liu, Tenko Yamashita | 2016-12-13 |
| 9515194 | Nano-ribbon channel transistor with back-bias control | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2016-12-06 |
| 9514997 | Silicon-germanium FinFET device with controlled junction | Pouya Hashemi, Kam-Leung Lee, Alexander Reznicek | 2016-12-06 |
| 9515089 | Bulk fin formation with vertical fin sidewall profile | Hong He, Sivananda K. Kanakasabapathy, Chiahsun Tseng, Yunpeng Yin | 2016-12-06 |
| 9515140 | Patterned strained semiconductor substrate and device | Ramachandra Divakaruni | 2016-12-06 |
| 9515173 | Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-12-06 |
| 9508829 | Nanosheet MOSFET with full-height air-gap spacer | Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2016-11-29 |
| 9508851 | Formation of bulk SiGe fin with dielectric isolation by anodization | Thomas N. Adam, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-11-29 |
| 9508587 | Formation of isolation surrounding well implantation | Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2016-11-29 |
| 9508810 | FET with air gap spacer for improved overlap capacitance | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-11-29 |
| 9508818 | Method and structure for forming gate contact above active area with trench silicide | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2016-11-29 |
| 9508825 | Method and structure for forming gate contact above active area with trench silicide | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2016-11-29 |