Issued Patents 2016
Showing 1–25 of 185 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530843 | FinFET having an epitaxially grown semiconductor on the fin in the channel region | Thomas N. Adam, Kangguo Cheng, Alexander Reznicek, Davood Shahrjerdi | 2016-12-27 |
| 9530775 | Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices | Xiuyu Cai, Ruilong Xie, Kangguo Cheng | 2016-12-27 |
| 9525027 | Lateral bipolar junction transistor having graded SiGe base | Pouya Hashemi, Darsen D. Lu, Alexander Reznicek, Dominic J. Schepis | 2016-12-20 |
| 9520328 | Type III-V and type IV semiconductor device formation | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-12-13 |
| 9520397 | Abrupt source/drain junction formation using a diffusion facilitation layer | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-12-13 |
| 9515171 | Radiation tolerant device structure | Bruce B. Doris, Darsen D. Lu, Philip J. Oldiges | 2016-12-06 |
| 9515173 | Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-12-06 |
| 9508851 | Formation of bulk SiGe fin with dielectric isolation by anodization | Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-11-29 |
| 9508741 | CMOS structure on SSOI wafer | Bruce B. Doris, Hong He, Junli Wang | 2016-11-29 |
| 9508810 | FET with air gap spacer for improved overlap capacitance | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-11-29 |
| 9502245 | Elimination of defects in long aspect ratio trapping trench structures | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-11-22 |
| 9502243 | Multi-orientation SOI substrates for co-integration of different conductivity type semiconductor devices | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-11-22 |
| 9496373 | Damage-resistant fin structures and FinFET CMOS | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-11-15 |
| 9496282 | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition | Thomas N. Adam, Kangguo Cheng, Alexander Reznicek, Raghavasimhan Sreenivasan | 2016-11-15 |
| 9496343 | Secondary use of aspect ratio trapping holes as eDRAM structure | Kangguo Cheng, Bruce B. Doris, Alexander Reznicek | 2016-11-15 |
| 9496356 | Under-spacer doping in fin-based semiconductor devices | Veeraraghavan S. Basker, Kangguo Cheng, Charles W. Koburger, III | 2016-11-15 |
| 9496281 | Dual isolation on SSOI wafer | Bruce B. Doris, Hong He, Junli Wang | 2016-11-15 |
| 9484359 | MOSFET with work function adjusted metal backgate | Kangguo Cheng, Bruce B. Doris, Pranita Kerber | 2016-11-01 |
| 9484348 | Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs | Veeraraghavan S. Basker, Kangguo Cheng | 2016-11-01 |
| 9484430 | Back-end transistors with highly doped low-temperature contacts | Wilfried E. Haensch, Bahman Hekmatshoar-Tabari, Tak H. Ning, Ghavam G. Shahidi, Davood Shahrjerdi | 2016-11-01 |
| 9484464 | Structure and method for adjusting threshold voltage of the array of transistors | Jin Cai, Kangguo Cheng, Robert H. Dennard, Tak H. Ning | 2016-11-01 |
| 9478658 | Device and method for fabricating thin semiconductor channel and buried strain memorization layer | Kangguo Cheng, Bruce B. Doris, Pranita Kulkarni, Ghavam G. Shahidi | 2016-10-25 |
| 9478468 | Dual metal contact scheme for CMOS devices | Kangguo Cheng, Alexander Reznicek, Tenko Yamashita | 2016-10-25 |
| 9472628 | Heterogeneous source drain region and extension region | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-10-18 |
| 9472558 | Semiconductor structures with stacked non-planar field effect transistors and methods of forming the structures | Kangguo Cheng, Carl Radens, Robert C. Wong | 2016-10-18 |