Issued Patents 2016
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530699 | Semiconductor device including gate channel having adjusted threshold voltage | Qiqing C. Ouyang, Alexander Reznicek | 2016-12-27 |
| 9530860 | III-V MOSFETs with halo-doped bottom barrier layer | Chung-Hsun Lin, Amlan Majumdar, Jeffrey W. Sleight | 2016-12-27 |
| 9515165 | III-V field effect transistor (FET) with reduced short channel leakage, integrated circuit (IC) chip and method of manufacture | Cheng-Wei Cheng, Effendi Leobandung, Amlan Majumdar | 2016-12-06 |
| 9502408 | FinFET device including fins having a smaller thickness in a channel region, and a method of manufacturing same | Qiqing C. Ouyang, Alexander Reznicek | 2016-11-22 |
| 9502420 | Structure and method for highly strained germanium channel fins for high mobility pFINFETs | Stephen W. Bedell, Lisa F. Edge, Qiqing C. Ouyang, Alexander Reznicek | 2016-11-22 |
| 9484359 | MOSFET with work function adjusted metal backgate | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz | 2016-11-01 |
| 9484412 | Strained silicon—germanium integrated circuit with inversion capacitance enhancement and method to fabricate same | Takashi Ando, Pouya Hashemi, Alexander Reznicek | 2016-11-01 |
| 9472553 | High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material | Takashi Ando, Martin M. Frank, Vijay Narayanan | 2016-10-18 |
| 9460243 | Selective importance sampling | Rajiv V. Joshi, Rouwaida N. Kanj | 2016-10-04 |
| 9443940 | Defect reduction with rotated double aspect ratio trapping | Keith E. Fogel, Judson R. Holt, Alexander Reznicek | 2016-09-13 |
| 9443963 | SiGe FinFET with improved junction doping control | Qiqing C. Ouyang, Alexander Reznicek | 2016-09-13 |
| 9443873 | Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step | Qiqing C. Ouyang, Alexander Reznicek, Dominic J. Schepis | 2016-09-13 |
| 9412865 | Reduced resistance short-channel InGaAs planar MOSFET | Qiqing C. Ouyang, Alexander Reznicek | 2016-08-09 |
| 9397161 | Reduced current leakage semiconductor device | Cheng-Wei Cheng, Young-Hee Kim, Effendi Leobandung, Yanning Sun | 2016-07-19 |
| 9391198 | Strained semiconductor trampoline | Qiqing C. Ouyang, Alexander Reznicek, Dominic J. Schepis | 2016-07-12 |
| 9391091 | MOSFET with work function adjusted metal backgate | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz | 2016-07-12 |
| 9391173 | FinFET device with vertical silicide on recessed source/drain epitaxy regions | Keith E. Fogel, Qiqing C. Ouyang, Alexander Reznicek | 2016-07-12 |
| 9385237 | Source and drain doping profile control employing carbon-doped semiconductor material | Viorel Ontalus, Donald R. Wall, Zhengmao Zhu | 2016-07-05 |
| 9379219 | SiGe finFET with improved junction doping control | Qiqing C. Ouyang, Alexander Reznicek | 2016-06-28 |
| 9362282 | High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material | Takashi Ando, Martin M. Frank, Vijay Narayanan | 2016-06-07 |
| 9356119 | MOSFETs with reduced contact resistance | Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz | 2016-05-31 |
| 9356019 | Integrated circuit with on chip planar diode and CMOS devices | Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi | 2016-05-31 |
| 9337259 | Structure and method to improve ETSOI MOSFETS with back gate | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Balasubramanian Pranatharthiharan | 2016-05-10 |
| 9293464 | Structure to enhance gate induced strain effect in multigate devices | Veeraraghavan S. Basker, Junli Wang, Tenko Yamashita, Chun-Chen Yeh | 2016-03-22 |
| 9275908 | Semiconductor device including gate channel having adjusted threshold voltage | Qiqing C. Ouyang, Alexander Reznicek | 2016-03-01 |