Issued Patents 2016
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530890 | Parasitic capacitance reduction | Junli Wang | 2016-12-27 |
| 9520500 | Self heating reduction for analog radio frequency (RF) device | Injo Ok, Charan V. Surisetty, Soon-Cheon Seo, Tenko Yamashita | 2016-12-13 |
| 9515163 | Methods of forming FinFET semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices | Ruilong Xie, Shom Ponoth | 2016-12-06 |
| 9508816 | Low resistance replacement metal gate structure | Injo Ok, Charan V. Surisetty | 2016-11-29 |
| 9502418 | Semiconductor devices with sidewall spacers of equal thickness | Kangguo Cheng, Soon-Cheon Seo | 2016-11-22 |
| 9496133 | Method to prevent lateral epitaxial growth in semiconductor devices by performing nitridation process on exposed Fin ends | Hui Zang | 2016-11-15 |
| 9484401 | Capacitance reduction for advanced technology nodes | Injo Ok, Charan V. Surisetty | 2016-11-01 |
| 9472616 | Undercut insulating regions for silicon-on-insulator device | Kangguo Cheng, Bruce B. Doris, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2016-10-18 |
| 9472447 | Confined eptaxial growth for continued pitch scaling | Sivananda K. Kanakasabapathy | 2016-10-18 |
| 9466680 | Integrated multiple gate length semiconductor device including self-aligned contacts | Su Chen Fan, Rajasekhar Venigalla | 2016-10-11 |
| 9461168 | Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2016-10-04 |
| 9443738 | Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods | Hui Zang | 2016-09-13 |
| 9443944 | Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods | Hui Zang | 2016-09-13 |
| 9443853 | Minimizing shorting between FinFET epitaxial regions | Kangguo Cheng, Alexander Reznicek, Charan V. Surisetty | 2016-09-13 |
| 9437504 | Method for the formation of fin structures for FinFET devices | Nicolas Loubet, Prasanna Khare, Qing Liu, Shom Ponoth | 2016-09-06 |
| 9431486 | Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2016-08-30 |
| 9431399 | Method for forming merged contact for semiconductor device | Emre Alptekin, Sivananda K. Kanakasabapathy, Ravikumar Ramachandran, Mickey H. Yu | 2016-08-30 |
| 9425108 | Method to prevent lateral epitaxial growth in semiconductor devices | Hui Zang | 2016-08-23 |
| 9419097 | Replacement metal gate dielectric cap | Damon B. Farmer, Michael A. Guillorn, George S. Tulevski | 2016-08-16 |
| 9418902 | Forming isolated fins from a substrate | Kangguo Cheng, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2016-08-16 |
| 9406767 | POC process flow for conformal recess fill | Andrew M. Greene, Sanjay C. Mehta, Ruilong Xie | 2016-08-02 |
| 9406568 | Semiconductor structure containing low-resistance source and drain contacts | Injo Ok, Charan V. Surisetty | 2016-08-02 |
| 9397006 | Co-integration of different fin pitches for logic and analog devices | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2016-07-19 |
| 9349598 | Gate contact with vertical isolation from source-drain | David V. Horak, Shom Ponoth, Ruilong Xie | 2016-05-24 |
| 9337094 | Method of forming contact useful in replacement metal gate processing and related semiconductor structure | Injo Ok, Charan V. Surisetty | 2016-05-10 |