Issued Patents 2016
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530777 | FinFETs of different compositions formed on a same substrate | Hong He, James Kuss | 2016-12-27 |
| 9520393 | Fully substrate-isolated FinFET transistor | Prasanna Khare | 2016-12-13 |
| 9502292 | Dual shallow trench isolation liner for preventing electrical shorts | Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Maud Vinet | 2016-11-22 |
| 9466720 | Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer | Qing Liu | 2016-10-11 |
| 9466718 | Semiconductor device with fin and related methods | Pierre Morin | 2016-10-11 |
| 9460971 | Method to co-integrate oppositely strained semiconductor devices on a same substrate | Sylvain Maitrejean, Romain Wacquez | 2016-10-04 |
| 9461174 | Method for the formation of silicon and silicon-germanium fin structures for FinFET devices | Hong He, James Kuss | 2016-10-04 |
| 9437504 | Method for the formation of fin structures for FinFET devices | Prasanna Khare, Qing Liu, Balasubramanian Pranatharthiharan, Shom Ponoth | 2016-09-06 |
| 9437474 | Method for fabricating microelectronic devices with isolation trenches partially formed under active regions | Laurent Grenouillet, Yannick Le Tiec, Maud Vinet, Romain Wacquez | 2016-09-06 |
| 9419111 | Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods | Qing Liu, Prasanna Khare | 2016-08-16 |
| 9418900 | Silicon germanium and silicon fins on oxide from bulk wafer | Hong He, James Kuss, Junli Wang | 2016-08-16 |
| 9406783 | Method to induce strain in finFET channels from an adjacent region | Pierre Morin | 2016-08-02 |
| 9396984 | Method of producing a microelectronic device in a monocrystalline semiconductor substrate with isolation trenches partially formed under an active region | Maud Vinet, Romain Wacquez | 2016-07-19 |
| 9385051 | Method for the formation of a FinFET device having partially dielectric isolated fin structure | Ronald K. Sampson | 2016-07-05 |
| 9368411 | Method for the formation of fin structures for FinFET devices | Qing Liu | 2016-06-14 |
| 9349730 | Fin transformation process and isolation structures facilitating different Fin isolation schemes | Ajey Poovannummoottil Jacob, Kangguo Cheng, Bruce B. Doris, Prasanna Khare, Ramachandra Divakaruni | 2016-05-24 |
| 9337079 | Prevention of contact to substrate shorts | Qing Liu, Shom Ponoth | 2016-05-10 |
| 9263343 | Dual EPI CMOS integration for planar substrates | Balasubramanian Pranatharthiharan | 2016-02-16 |
| 9263580 | Methods of forming isolated channel regions for a FinFET semiconductor device and the resulting device | Ajey Poovannummoottil Jacob | 2016-02-16 |
| 9257450 | Semiconductor device including groups of stacked nanowires and related methods | James Kuss | 2016-02-09 |
| 9252052 | Dual shallow trench isolation liner for preventing electrical shorts | Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Maud Vinet | 2016-02-02 |
| 9245953 | Method to induce strain in 3-D microfabricated structures | Pierre Morin | 2016-01-26 |
| 9236380 | Semiconductor-on-insulator (SOI) device and related methods for making same using non-oxidizing thermal treatment | Pierre Morin, Qing Liu | 2016-01-12 |
| 9230991 | Method to co-integrate oppositely strained semiconductor devices on a same substrate | Sylvain Maitrejean, Romain Wacquez | 2016-01-05 |