Issued Patents 2016
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9502292 | Dual shallow trench isolation liner for preventing electrical shorts | Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Nicolas Loubet | 2016-11-22 |
| 9466664 | Uniaxially-strained FD-SOI finFET | Pierre Morin, Laurent Grenouillet, Ajey Poovannummoottil Jacob | 2016-10-11 |
| 9443933 | Matching of transistors | Frédéric Allibert | 2016-09-13 |
| 9437475 | Method for fabricating microelectronic devices with isolation trenches partially formed under active regions | Sylvie Mignot, Romain Wacquez | 2016-09-06 |
| 9437474 | Method for fabricating microelectronic devices with isolation trenches partially formed under active regions | Laurent Grenouillet, Yannick Le Tiec, Nicolas Loubet, Romain Wacquez | 2016-09-06 |
| 9425051 | Method for producing a silicon-germanium film with variable germanium content | Laurent Grenouillet, Yves Morand | 2016-08-23 |
| 9396984 | Method of producing a microelectronic device in a monocrystalline semiconductor substrate with isolation trenches partially formed under an active region | Nicolas Loubet, Romain Wacquez | 2016-07-19 |
| 9379213 | Method for forming doped areas under transistor spacers | Perrine Batude, Jean-Michel Hartmann, Benoit Sklenard | 2016-06-28 |
| 9373507 | Defective P-N junction for backgated fully depleted silicon on insulator mosfet | Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec +1 more | 2016-06-21 |
| 9337350 | Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same | Nicolas Posseme, Laurent Grenouillet, Yannick Le Tiec | 2016-05-10 |
| 9293474 | Dual channel hybrid semiconductor-on-insulator semiconductor devices | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Laurent Grenouillet +1 more | 2016-03-22 |
| 9252208 | Uniaxially-strained FD-SOI finFET | Pierre Morin, Laurent Grenouillet, Ajey Poovannummoottil Jacob | 2016-02-02 |
| 9252052 | Dual shallow trench isolation liner for preventing electrical shorts | Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Nicolas Loubet | 2016-02-02 |
| 9236478 | Method for manufacturing a fin MOS transistor | Yves Morand, Romain Wacquez, Laurent Grenouillet, Yannick Le Tiec | 2016-01-12 |
| 9231062 | Method for treating the surface of a silicon substrate | Yannick Le Tiec, Laurent Grenouillet, Romain Wacquez | 2016-01-05 |