Issued Patents 2016
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9514995 | Implant-free punch through doping layer formation for bulk FinFET structures | Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis | 2016-12-06 |
| 9508640 | Multiple via structure and method | Cheng-Wei Cheng, Szu-Lin Cheng, Edward W. Kiewra, Amlan Majumdar, Devendra K. Sadana +2 more | 2016-11-29 |
| 9502609 | Simplified process for vertical LED manufacturing | Stephen W. Bedell, Paul A. Lauro, Devendra K. Sadana | 2016-11-22 |
| 9502540 | Uniform height tall fins with varying silicon germanium concentrations | Stephen W. Bedell, Bruce B. Doris, Alexander Reznicek | 2016-11-22 |
| 9502278 | Substrate holder assembly for controlled layer transfer | Stephen W. Bedell, Paul A. Lauro, Devendra K. Sadana | 2016-11-22 |
| 9496186 | Uniform height tall fins with varying silicon germanium concentrations | Stephen W. Bedell, Bruce B. Doris, Alexander Reznicek | 2016-11-15 |
| 9496401 | III-V device structure with multiple threshold voltage | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-11-15 |
| 9490455 | LED light extraction enhancement enabled using self-assembled particles patterned surface | Jeehwan Kim, Ning Li, Devendra K. Sadana | 2016-11-08 |
| 9466672 | Reduced defect densities in graded buffer layers by tensile strained interlayers | Kangguo Cheng, Pouya Hashemi, John A. Ott, Alexander Reznicek | 2016-10-11 |
| 9443940 | Defect reduction with rotated double aspect ratio trapping | Judson R. Holt, Pranita Kerber, Alexander Reznicek | 2016-09-13 |
| 9419138 | Embedded carbon-doped germanium as stressor for germanium nFET devices | Jeffrey L. Dittmar, Sebastian Naczas, Alexander Reznicek, Devendra K. Sadana | 2016-08-16 |
| 9404942 | Coaxial probe structure of elongated electrical conductors projecting from a support structure | Brian S. Beaman, Paul A. Lauro, Yun-Hsin Liao, Daniel Peter Morris, Da-Yuan Shih | 2016-08-02 |
| 9406506 | Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-08-02 |
| 9394178 | Wafer scale epitaxial graphene transfer | Stephen W. Bedell, Christos D. Dimitrakopoulos, James B. Hannon, Jeehwan Kim, Hongsik Park +2 more | 2016-07-19 |
| 9391173 | FinFET device with vertical silicide on recessed source/drain epitaxy regions | Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek | 2016-07-12 |
| 9379204 | Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-06-28 |
| 9373741 | Heterostructure germanium tandem junction solar cell | Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi | 2016-06-21 |
| 9337274 | Formation of large scale single crystalline graphene | Christos D. Dimitrakopoulos, Jeehwan Kim, Hongsik Park | 2016-05-10 |
| 9337436 | Transferable transparent conductive oxide | Jeehwan Kim, Devendra K. Sadana, Tze-bin Song | 2016-05-10 |
| 9331220 | Three-dimensional conductive electrode for solar cell | Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana | 2016-05-03 |
| 9324813 | Doped zinc oxide as N+ layer for semiconductor devices | Joel P. Desouza, Jeehwan Kim, Ko-Tao Lee, Devendra K. Sadana | 2016-04-26 |
| 9324564 | Spalling with laser-defined spall edge regions | Ibrahim Alhomoudi, Stephen W. Bedell, Cheng-Wei Cheng, Devendra K. Sadana, Katherine L. Saenger +2 more | 2016-04-26 |
| 9318641 | Nanowires formed by employing solder nanodots | Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana, Kuen-Ting Shiu | 2016-04-19 |
| 9308714 | Method for improving surface quality of spalled substrates | Stephen W. Bedell, Paul A. Lauro, Devendra K. Sadana | 2016-04-12 |
| 9275867 | Method for improving quality of spalled material layers | Stephen W. Bedell, Paul A. Lauro, Ning Li, Devendra K. Sadana, Katherine L. Saenger +1 more | 2016-03-01 |