Issued Patents 2004
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6828199 | Monos device having buried metal silicide bit line | Jusuke Ogura, Mark T. Ramsbey, Zoran Krivokapic, Minh Van Ngo, Nicholas H. Tripisas | 2004-12-07 |
| 6828162 | System and method for active control of BPSG deposition | Bhanwar Singh, Michael K. Templeton, Ramkumar Subramanian | 2004-12-07 |
| 6815229 | In situ monitoring of sheet resistivity of silicides during rapid thermal annealing using electrical methods | Ramkumar Subramanian, Bhanwar Singh | 2004-11-09 |
| 6803265 | Liner for semiconductor memories and manufacturing method therefor | Minh Van Ngo, Tazrien Kamal, Hidehiko Shiraiwa, Rinji Sugino, Dawn Hopper +1 more | 2004-10-12 |
| 6803275 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Jaeyong Park, Hidehiko Shiraiwa, Jean Y. Yang, Inkuk Kang, Tazrien Kamal +1 more | 2004-10-12 |
| 6803272 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Mark T. Ramsbey, Kuo-Tung Chang, Nicholas H. Tripsas, Robert B. Ogle | 2004-10-12 |
| 6783591 | Laser thermal annealing method for high dielectric constant gate oxide films | Nicholas H. Tripsas, Mark T. Ramsbey | 2004-08-31 |
| 6774989 | Interlayer dielectric void detection | Bharath Rangarajan, Michael K. Templeton, Bhanwar Singh | 2004-08-10 |
| 6774432 | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL | Minh Van Ngo, Tazrien Kamal, Mark T. Ramsbey, Jaeyong Park, Ning Cheng +6 more | 2004-08-10 |
| 6770523 | Method for semiconductor wafer planarization by CMP stop layer formation | Kashmir Sahota, Jeffrey P. Erhardt, Minh Van Ngo, Krishnashree Achuthan | 2004-08-03 |
| 6764966 | Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric | William G. En, Ming-Ren Lin, Minh Van Ngo, Chih-Yuh Yang | 2004-07-20 |
| 6762454 | Stacked polysilicon layer for boron penetration inhibition | Effiong Ibok, Joong S. Jeon, Minh Van Ngo | 2004-07-13 |
| 6753261 | In-situ chemical composition monitor on wafer during plasma etching for defect control | Khoi A. Phan, Bhanwar Singh | 2004-06-22 |
| 6752899 | Acoustic microbalance for in-situ deposition process monitoring and control | Bhanwar Singh, Michael K. Templeton | 2004-06-22 |
| 6750066 | Precision high-K intergate dielectric layer | Fred Cheung | 2004-06-15 |
| 6740605 | Process for reducing hydrogen contamination in dielectric materials in memory devices | Hidehiko Shiraiwa, Jaeyong Park, Fred Cheung | 2004-05-25 |
| 6731006 | Doped copper interconnects using laser thermal annealing | Minh Van Ngo | 2004-05-04 |
| 6727995 | Gate oxide thickness measurement and control using scatterometry | Bhanwar Singh, Ramkumar Subramanian | 2004-04-27 |
| 6727176 | Method of forming reliable Cu interconnects | Minh Van Ngo, Eric N. Paton | 2004-04-27 |
| 6721046 | Monitoring of concentration of nitrogen in nitrided gate oxides, and gate oxide interfaces | Bhanwar Singh, Ramkumar Subramanian | 2004-04-13 |
| 6716702 | Method of forming flash memory having pre-interpoly dielectric treatment layer | Robert B. Ogle | 2004-04-06 |
| 6709927 | Process for treating ONO dielectric film of a floating gate memory cell | Robert B. Ogle | 2004-03-23 |
| 6693004 | Interfacial barrier layer in semiconductor devices with high-K gate dielectric material | Joong S. Jeon, Minh Van Ngo, William G. En, Effiong Ibok | 2004-02-17 |
| 6693321 | Replacing layers of an intergate dielectric layer with high-K material for improved scalability | Wei Zheng, Mark Randolph | 2004-02-17 |
| 6674138 | Use of high-k dielectric materials in modified ONO structure for semiconductor devices | Mark T. Ramsbey, Kuo-Tung Chang, Nicholas H. Tripsas, Robert B. Ogle | 2004-01-06 |