Issued Patents 2004
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6813752 | Method of determining charge loss activation energy of a memory array | Edward Hsia, Darlene Hamilton, Mark Randolph, Kulachet Tanpairoj | 2004-11-02 |
| 6782350 | Method and apparatus for managing resources | Christopher Burnley, Brian Gerhold, Pamela Day, Mike Sherman | 2004-08-24 |
| 6754105 | Trench side wall charge trapping dielectric flash memory device | Chi Chang, Hidehiko Shiraiwa | 2004-06-22 |
| 6744675 | Program algorithm including soft erase for SONOS memory device | Mark Randolph | 2004-06-01 |
| 6743677 | Method for fabricating nitride memory cells using a floating gate fabrication process | Mark Randolph, Darlene Hamilton, Binh Quang Le | 2004-06-01 |
| 6735123 | High density dual bit flash memory cell with non planar structure | Nicholas H. Tripsas, Mark T. Ramsbey, Effiong Ibok, Fred Cheung | 2004-05-11 |
| 6716698 | Virtual ground silicide bit line process for floating gate flash memory | Yue-Song He, Richard Fastow | 2004-04-06 |
| 6693321 | Replacing layers of an intergate dielectric layer with high-K material for improved scalability | Arvind Halliyal, Mark Randolph | 2004-02-17 |