Issued Patents 2004
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833297 | Method for reducing drain induced barrier lowering in a memory device | Yue-Song He, Nga-Ching Wong | 2004-12-21 |
| 6819615 | Memory device having resistive element coupled to reference cell for improved reliability | Wing Leung, John Wang | 2004-11-16 |
| 6781885 | Method of programming a memory cell | Sheung-Hee Park, Wing Leung | 2004-08-24 |
| 6773990 | Method for reducing short channel effects in memory cells and related structure | Yue-Song He, Kazuhiro Mizutani, Timothy Thurgate | 2004-08-10 |
| 6768683 | Low column leakage flash memory array | Sameer Haddad | 2004-07-27 |
| 6754109 | Method of programming memory cells | Sameer Haddad, Zhigang Wang, Sheung-Hee Park | 2004-06-22 |
| 6750157 | Nonvolatile memory cell with a nitridated oxide layer | Chi Chang, Narbeh Derhacobian | 2004-06-15 |
| 6737703 | Memory array with buried bit lines | Sameer Haddad, Yu Sun | 2004-05-18 |
| 6716698 | Virtual ground silicide bit line process for floating gate flash memory | Yue-Song He, Wei Zheng | 2004-04-06 |
| 6700201 | Reduction of sector connecting line capacitance using staggered metal lines | Yue-Song He, Sameer Haddad | 2004-03-02 |