Issued Patents 2004
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6808996 | Method for protecting gate edges from charge gain/loss in semiconductor device | Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Chi Chang | 2004-10-26 |
| 6808992 | Method and system for tailoring core and periphery cells in a nonvolatile memory | Kelwin Ko, Shenqing Fang, Angela T. Hui, Hiroyuki Kinoshita, Wenmei Li +1 more | 2004-10-26 |
| 6787840 | Nitridated tunnel oxide barriers for flash memory technology circuitry | Tuan Pham, Mark T. Ramsbey, Chi Chang | 2004-09-07 |
| 6780708 | METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY | Hiroyuki Kinoshita, Basab Banerjee, Christopher Foster, John R. Behnke, Cyrus E. Tabery | 2004-08-24 |
| 6737703 | Memory array with buried bit lines | Richard Fastow, Sameer Haddad | 2004-05-18 |
| 6730564 | Salicided gate for virtual ground arrays | Mark T. Ramsbey, Chi Chang, Hidehiko Shiraiwa | 2004-05-04 |
| 6727143 | Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation | Angela T. Hui, Mark T. Ramsbey, David Matsumoto | 2004-04-27 |
| 6680509 | Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory | Yider Wu, Jean Y. Yang, Mark T. Ramsbey, Emmanuel H. Lingunis | 2004-01-20 |