Issued Patents 2004
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6836398 | System and method of forming a passive layer by a CMP process | Ramkumar Subramanian, Jane V. Oglesby, Minh Van Ngo, Mark S. Chang, Sergey Lopatin +3 more | 2004-12-28 |
| 6833581 | Structure and method for preventing process-induced UV radiation damage in a memory cell | Minh Van Ngo, Ning Cheng, Jaeyong Park, Jean Y. Yang, Kouros Ghandehari +1 more | 2004-12-21 |
| 6809033 | Innovative method of hard mask removal | Jusuke Ogura | 2004-10-26 |
| 6808996 | Method for protecting gate edges from charge gain/loss in semiconductor device | Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Yu Sun, Chi Chang | 2004-10-26 |
| 6808992 | Method and system for tailoring core and periphery cells in a nonvolatile memory | Kelwin Ko, Shenqing Fang, Hiroyuki Kinoshita, Wenmei Li, Yu Sun +1 more | 2004-10-26 |
| 6803267 | Silicon containing material for patterning polymeric memory element | Ramkumar Subramanian, Christopher F. Lyons, Matthew S. Buynoski, Patrick K. Cheung, Ashok M. Khathuria +5 more | 2004-10-12 |
| 6787458 | Polymer memory device formed in via opening | Nicholas H. Tripsas, Matthew S. Buynoski, Suzette K. Pangrle, Uzodinma Okoroanyanwu, Christopher F. Lyons +7 more | 2004-09-07 |
| 6774432 | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL | Minh Van Ngo, Tazrien Kamal, Mark T. Ramsbey, Arvind Halliyal, Jaeyong Park +6 more | 2004-08-10 |
| 6764929 | Method and system for providing a contact hole in a semiconductor device | Chi Chang, Mark S. Chang | 2004-07-20 |
| 6765254 | Structure and method for preventing UV radiation damage and increasing data retention in memory cells | Minh Van Ngo, Ning Cheng, Jaeyong Park, Jean Y. Yang, Hidehiko Shiraiwa +3 more | 2004-07-20 |
| 6753247 | Method(s) facilitating formation of memory cell(s) and patterned conductive | Uzodinma Okoroanyanwu, Suzette K. Pangrle, Matthew S. Buynoski, Nicholas H. Tripsas, Mark S. Chang +1 more | 2004-06-22 |
| 6727143 | Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation | Mark T. Ramsbey, Yu Sun, David Matsumoto | 2004-04-27 |
| 6713809 | Dual bit memory device with isolated polysilicon floating gates | Jusuke Ogura, Kazuhiro Kurihara, Masaru Yano, Hideki Komori, Tuan Pham | 2004-03-30 |
| 6706576 | Laser thermal annealing of silicon nitride for increased density and etch selectivity | Minh Van Ngo | 2004-03-16 |
| 6680507 | Dual bit isolation scheme for flash memory devices having polysilicon floating gates | Tuan Pham | 2004-01-20 |