Issued Patents 2004
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6808996 | Method for protecting gate edges from charge gain/loss in semiconductor device | Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Yu Sun | 2004-10-26 |
| 6806155 | Method and system for scaling nonvolatile memory cells | Kelwin Ko | 2004-10-19 |
| 6787840 | Nitridated tunnel oxide barriers for flash memory technology circuitry | Tuan Pham, Mark T. Ramsbey, Yu Sun | 2004-09-07 |
| 6764929 | Method and system for providing a contact hole in a semiconductor device | Angela T. Hui, Mark S. Chang | 2004-07-20 |
| 6754105 | Trench side wall charge trapping dielectric flash memory device | Wei Zheng, Hidehiko Shiraiwa | 2004-06-22 |
| 6750157 | Nonvolatile memory cell with a nitridated oxide layer | Richard Fastow, Narbeh Derhacobian | 2004-06-15 |
| 6744668 | Flash memory array with dual function control lines and asymmetrical source and drain junctions | Michael A. Van Buskirk | 2004-06-01 |
| 6730564 | Salicided gate for virtual ground arrays | Mark T. Ramsbey, Yu Sun, Hidehiko Shiraiwa | 2004-05-04 |
| 6701406 | PCI and MII compatible home phoneline networking alliance (HPNA) interface device | Chin-Wei Liang, Matthew James Fischer | 2004-03-02 |