Issued Patents 2004
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6828199 | Monos device having buried metal silicide bit line | Jusuke Ogura, Arvind Halliyal, Zoran Krivokapic, Minh Van Ngo, Nicholas H. Tripisas | 2004-12-07 |
| 6808996 | Method for protecting gate edges from charge gain/loss in semiconductor device | Tuan Pham, Sameer Haddad, Angela T. Hui, Yu Sun, Chi Chang | 2004-10-26 |
| 6803272 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Arvind Halliyal, Kuo-Tung Chang, Nicholas H. Tripsas, Robert B. Ogle | 2004-10-12 |
| 6798002 | Dual-purpose anti-reflective coating and spacer for flash memory and other dual gate technologies and method of forming | Robert B. Ogle, Tuan Pham | 2004-09-28 |
| 6794764 | Charge-trapping memory arrays resistant to damage from contact hole information | Tazrien Kamal, Hidehiko Shiraiwa, Fred Cheung | 2004-09-21 |
| 6787840 | Nitridated tunnel oxide barriers for flash memory technology circuitry | Tuan Pham, Yu Sun, Chi Chang | 2004-09-07 |
| 6783591 | Laser thermal annealing method for high dielectric constant gate oxide films | Arvind Halliyal, Nicholas H. Tripsas | 2004-08-31 |
| 6774432 | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL | Minh Van Ngo, Tazrien Kamal, Arvind Halliyal, Jaeyong Park, Ning Cheng +6 more | 2004-08-10 |
| 6773988 | Memory wordline spacer | Kashmir Sahota, Tazrien Kamal | 2004-08-10 |
| 6770938 | Diode fabrication for ESD/EOS protection | Michael Fliesler, Mark Randolph, Ian Morgan, Timothy Thurgate, Paohua Kuo +1 more | 2004-08-03 |
| 6753570 | Memory device and method of making | Nicholas H. Tripsas, Kuo-Tung Chang | 2004-06-22 |
| 6735123 | High density dual bit flash memory cell with non planar structure | Nicholas H. Tripsas, Wei Zheng, Effiong Ibok, Fred Cheung | 2004-05-11 |
| 6730564 | Salicided gate for virtual ground arrays | Yu Sun, Chi Chang, Hidehiko Shiraiwa | 2004-05-04 |
| 6727143 | Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation | Angela T. Hui, Yu Sun, David Matsumoto | 2004-04-27 |
| 6720133 | Memory manufacturing process using disposable ARC for wordline formation | Kouros Ghandehari, Tazrien Kamal, Jean Y. Yang, Emmanuil H. Lingunis, Hidehiko Shiraiwa | 2004-04-13 |
| 6706595 | Hard mask process for memory device without bitline shorts | Jean Y. Yang, Hidehiko Shiraiwa, Yider Wu, Emmanuil Lingunis, Tazrien Kamal | 2004-03-16 |
| 6707078 | Dummy wordline for erase and bitline leakage | Hidehiko Shiraiwa, Yider Wu, Jean Y. Yang, Darlene Hamilton | 2004-03-16 |
| 6680509 | Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory | Yider Wu, Jean Y. Yang, Emmanuel H. Lingunis, Yu Sun | 2004-01-20 |
| 6674138 | Use of high-k dielectric materials in modified ONO structure for semiconductor devices | Arvind Halliyal, Kuo-Tung Chang, Nicholas H. Tripsas, Robert B. Ogle | 2004-01-06 |