Issued Patents 2004
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6803275 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Inkuk Kang, Tazrien Kamal +1 more | 2004-10-12 |
| 6797565 | Methods for fabricating and planarizing dual poly scalable SONOS flash memory | Yider Wu, Zhizheng Liu | 2004-09-28 |
| 6767791 | Structure and method for suppressing oxide encroachment in a floating gate memory cell | Yider Wu, Harpreet Sachar | 2004-07-27 |
| 6765254 | Structure and method for preventing UV radiation damage and increasing data retention in memory cells | Angela T. Hui, Minh Van Ngo, Ning Cheng, Jaeyong Park, Hidehiko Shiraiwa +3 more | 2004-07-20 |
| 6754106 | Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory | Yider Wu, Jiang Li | 2004-06-22 |
| 6744105 | Memory array having shallow bit line with silicide contact portion and method of formation | Cinti X. Chen, Hiroyuki Kinoshita, Jeff P. Erhardt, Weidong Qian | 2004-06-01 |
| 6737701 | Structure and method for reducing charge loss in a memory cell | Amy C. Tu, Yider Wu | 2004-05-18 |
| 6720133 | Memory manufacturing process using disposable ARC for wordline formation | Mark T. Ramsbey, Kouros Ghandehari, Tazrien Kamal, Emmanuil H. Lingunis, Hidehiko Shiraiwa | 2004-04-13 |
| 6707078 | Dummy wordline for erase and bitline leakage | Hidehiko Shiraiwa, Yider Wu, Mark T. Ramsbey, Darlene Hamilton | 2004-03-16 |
| 6706595 | Hard mask process for memory device without bitline shorts | Mark T. Ramsbey, Hidehiko Shiraiwa, Yider Wu, Emmanuil Lingunis, Tazrien Kamal | 2004-03-16 |
| 6680509 | Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory | Yider Wu, Mark T. Ramsbey, Emmanuel H. Lingunis, Yu Sun | 2004-01-20 |