Issued Patents 2004
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833297 | Method for reducing drain induced barrier lowering in a memory device | Richard Fastow, Nga-Ching Wong | 2004-12-21 |
| 6825526 | Structure for increasing drive current in a memory array and related method | Nian Yang, Zhigang Wang | 2004-11-30 |
| 6773990 | Method for reducing short channel effects in memory cells and related structure | Richard Fastow, Kazuhiro Mizutani, Timothy Thurgate | 2004-08-10 |
| 6723638 | Performance in flash memory devices | Sameer Haddad, Zhi-Gang Wang | 2004-04-20 |
| 6716698 | Virtual ground silicide bit line process for floating gate flash memory | Richard Fastow, Wei Zheng | 2004-04-06 |
| 6700201 | Reduction of sector connecting line capacitance using staggered metal lines | Richard Fastow, Sameer Haddad | 2004-03-02 |