NY

Nian Yang

AM AMD: 22 patents #8 of 1,035Top 1%
Overall (2004): #155 of 270,089Top 1%
22
Patents 2004

Issued Patents 2004

Showing 1–22 of 22 patents

Patent #TitleCo-InventorsDate
6828623 Floating gate memory device with homogeneous oxynitride tunneling dielectric Xin Guo, Zhigang Wang 2004-12-07
6825684 Hot carrier oxide qualification method Hyeon-Seag Kim, Amit P. Marathe, Tien-Chun Yang 2004-11-30
6825526 Structure for increasing drive current in a memory array and related method Yue-Song He, Zhigang Wang 2004-11-30
6825083 Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices John Jianshi Wang, Xin Guo, Tien-Chun Yang 2004-11-30
6822259 Method of detecting and distinguishing stack gate edge defects at the source or drain junction Zhigang Wang, Xin Guo 2004-11-23
6818462 METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED Tien-Chun Yang, Zhigang Wang 2004-11-16
6812514 High density floating gate flash memory and fabrication processes therefor Zhigang Wang, Hyeon-Seag Kim 2004-11-02
6808945 Method and system for testing tunnel oxide on a memory-related structure Zhigang Wang, Hsiao-Han Thio 2004-10-26
6797650 Flash memory devices with oxynitride dielectric as the charge storage media Zhigang Wang, John Jianshi Wang, Jiang Li 2004-09-28
6784061 Process to improve the Vss line formation for high density flash memory and related structure associated therewith John Jianshi Wang, Hyeon-Seag Kim 2004-08-31
6784682 Method of detecting shallow trench isolation corner thinning by electrical trapping Tien-Chun Yang, Hyeon-Seag Kim 2004-08-31
6777957 Test structure to measure interlayer dielectric effects and breakdown and detect metal defects in flash memories Zhigang Wang, John Jianshi Wang 2004-08-17
6764920 Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devices John Jianshi Wang, Unsoon Kim 2004-07-20
6759295 METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED Tien-Chun Yang, Zhigang Wang 2004-07-06
6756806 Method of determining location of gate oxide breakdown of MOSFET by measuring currents Zhigang Wang, Tien-Chun Yang 2004-06-29
6734080 Semiconductor isolation material deposition system and method John Jianshi Wang, Tien-Chun Yang 2004-05-11
6734028 Method of detecting shallow trench isolation corner thinning by electrical stress Tien-Chun Yang, Hyeon-Seag Kim 2004-05-11
6731130 Method of determining gate oxide thickness of an operational MOSFET Zhigang Wang, Tien-Chun Yang 2004-05-04
6717850 Efficient method to detect process induced defects in the gate stack of flash memory devices Jiang Li, Zhigang Wang, John Jianshi Wang 2004-04-06
6716710 Using a first liner layer as a spacer in a semiconductor device Hsiao-Han Thio, Zhigang Wang 2004-04-06
6696331 Method of protecting a stacked gate structure during fabrication Zhigang Wang, Hsiao-Han Thio 2004-02-24
6689666 Replacing a first liner layer with a thicker oxide layer when forming a semiconductor device Hsiao-Han Thio, Zhigang Wang 2004-02-10