Issued Patents 2004
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6830987 | Semiconductor device with a silicon-on-void structure and method of making the same | Mario Pelella, Srinath Krishnan, Witold P. Maszara | 2004-12-14 |
| 6812550 | Wafer pattern variation of integrated circuit fabrication | Eric N. Paton, Mario M. Pelella, Witold P. Maszara | 2004-11-02 |
| 6780776 | Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer | Wen-Jie Qi, John G. Pellerin, Mark W. Michael, Darin A. Chan | 2004-08-24 |
| 6764917 | SOI device with different silicon thicknesses | Darin A. Chan, John G. Pellerin, Mark W. Michael | 2004-07-20 |
| 6764898 | Implantation into high-K dielectric material after gate etch to facilitate removal | Joong S. Jeon, Minh Van Ngo, Ming-Ren Lin | 2004-07-20 |
| 6764966 | Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric | Arvind Halliyal, Ming-Ren Lin, Minh Van Ngo, Chih-Yuh Yang | 2004-07-20 |
| 6765227 | Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding | Bin Yu, Judy Xilin An, Concetta Riccobene | 2004-07-20 |
| 6723666 | Method for reducing gate oxide surface irregularities | Philip A. Fisher | 2004-04-20 |
| 6717212 | Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure | Dong-Hyuk Ju, Srinath Krishnan, Concetta Riccobene, Zoran Krivokapic, Judy Xilin An +1 more | 2004-04-06 |
| 6713819 | SOI MOSFET having amorphized source drain and method of fabrication | Dong-Hyuk Ju, Srinath Krishnan | 2004-03-30 |
| 6713357 | Method to reduce parasitic capacitance of MOS transistors | Hai Hong Wang, Mark W. Michael, Wen-Jie Qi, John G. Pellerin | 2004-03-30 |
| 6693004 | Interfacial barrier layer in semiconductor devices with high-K gate dielectric material | Arvind Halliyal, Joong S. Jeon, Minh Van Ngo, Effiong Ibok | 2004-02-17 |