Issued Patents 2004
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6812077 | Method for patterning narrow gate lines | Douglas J. Bonser, Mark S. Chang | 2004-11-02 |
| 6780776 | Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer | Wen-Jie Qi, John G. Pellerin, William G. En, Mark W. Michael | 2004-08-24 |
| 6764917 | SOI device with different silicon thicknesses | William G. En, John G. Pellerin, Mark W. Michael | 2004-07-20 |
| 6764947 | Method for reducing gate line deformation and reducing gate line widths in semiconductor devices | Douglas J. Bonser, Marina V. Plat, Marilyn I. Wright, Chih-Yuh Yang, Lu You +2 more | 2004-07-20 |
| 6764949 | Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication | Douglas J. Bonser, Marina V. Plat, Chih-Yuh Yang, Scott A. Bell, Philip A. Fisher +6 more | 2004-07-20 |
| 6750127 | Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance | Mark S. Chang, Chih-Yuh Yang, Lu You, Scott A. Bell, Srikanteswara Dakshina-Murthy +1 more | 2004-06-15 |