Issued Patents 2004
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6812077 | Method for patterning narrow gate lines | Darin A. Chan, Mark S. Chang | 2004-11-02 |
| 6797552 | Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices | Mark S. Chang, Marina V. Plat, Chih-Yuh Yang, Scott A. Bell, Srikanteswara Dakshina-Murthy | 2004-09-28 |
| 6773998 | Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning | Philip A. Fisher, Marina V. Plat, Chih-Yuh Yang, Christopher F. Lyons, Scott A. Bell +2 more | 2004-08-10 |
| 6764949 | Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication | Marina V. Plat, Chih-Yuh Yang, Scott A. Bell, Darin A. Chan, Philip A. Fisher +6 more | 2004-07-20 |
| 6764947 | Method for reducing gate line deformation and reducing gate line widths in semiconductor devices | Darin A. Chan, Marina V. Plat, Marilyn I. Wright, Chih-Yuh Yang, Lu You +2 more | 2004-07-20 |
| 6750127 | Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance | Mark S. Chang, Darin A. Chan, Chih-Yuh Yang, Lu You, Scott A. Bell +1 more | 2004-06-15 |
| 6734088 | Control of two-step gate etch process | Matthew A. Purdy, Scott Bushman, James H. Hussey, Jr. | 2004-05-11 |
| 6673635 | Method for alignment mark formation for a shallow trench isolation process | Kay Hellig, Srikanteswara Dakshina-Murthy | 2004-01-06 |