Issued Patents 2004
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6825115 | Post silicide laser thermal annealing to avoid dopant deactivation | Qi Xiang, Robert B. Ogle, Cyrus E. Tabery, Bin Yu | 2004-11-30 |
| 6812550 | Wafer pattern variation of integrated circuit fabrication | William G. En, Mario M. Pelella, Witold P. Maszara | 2004-11-02 |
| 6812106 | Reduced dopant deactivation of source/drain extensions using laser thermal annealing | Qi Xiang, Robert B. Ogle, Cyrus E. Tabery, Bin Yu | 2004-11-02 |
| 6811448 | Pre-cleaning for silicidation in an SMOS process | Paul R. Besser, Qi Xiang | 2004-11-02 |
| 6806172 | Physical vapor deposition of nickel | Christy Mei-Chu Woo, Susan Tover | 2004-10-19 |
| 6797614 | Nickel alloy for SMOS process silicidation | Paul R. Besser, Minh Van Ngo, Qi Xiang | 2004-09-28 |
| 6787864 | Mosfets incorporating nickel germanosilicided gate and methods for their formation | Qi Xiang, Paul R. Besser, Ming-Ren Lin, Minh Van Ngo, Haihong Wang | 2004-09-07 |
| 6784506 | Silicide process using high K-dielectrics | Qi Xiang, Paul R. Besser, Matthew S. Buynoski, John Foster, Paul L. King | 2004-08-31 |
| 6780789 | Laser thermal oxidation to form ultra-thin gate oxide | Bin Yu, Robert B. Ogle, Cyrus E. Tabery, Qi Xiang | 2004-08-24 |
| 6773978 | Methods for improved metal gate fabrication | Paul R. Besser, James Pan | 2004-08-10 |
| 6764912 | Passivation of nitride spacer | John Foster, Matthew S. Buynoski, Qi Xiang, Paul R. Besser, Paul L. King | 2004-07-20 |
| 6746944 | Low nisi/si interface contact resistance with preamorphizing and laser thermal annealing | Qi Xiang, Robert B. Ogle, Cyrus E. Tabery, Bin Yu | 2004-06-08 |
| 6743689 | Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions | Robert B. Ogle, Cyrus E. Tabery, Qi Xiang, Bin Yu | 2004-06-01 |
| 6730576 | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer | Haihong Wang, Paul R. Besser, Jung-Suk Goo, Minh Van Ngo, Qi Xiang | 2004-05-04 |
| 6727176 | Method of forming reliable Cu interconnects | Minh Van Ngo, Arvind Halliyal | 2004-04-27 |
| 6703277 | Reducing agent for high-K gate dielectric parasitic interfacial layer | Bin Yu | 2004-03-09 |
| 6703648 | Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication | Qi Xiang, Haihong Wang | 2004-03-09 |
| 6689688 | Method and device using silicide contacts for semiconductor processing | Paul R. Besser, Simon S. Chan, David E. Brown | 2004-02-10 |
| 6682973 | Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications | Qi Xiang, Bin Yu | 2004-01-27 |
| 6680250 | Formation of deep amorphous region to separate junction from end-of-range defects | Robert B. Ogle, Cyrus E. Tabery, Qi Xiang, Bin Yu | 2004-01-20 |