Issued Patents 2004
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833588 | Semiconductor device having a U-shaped gate structure | Bin Yu, Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Zoran Krivokapic | 2004-12-21 |
| 6812119 | Narrow fins by oxidation in double-gate finfet | Shibly S. Ahmed, Ming-Ren Lin, Bin Yu | 2004-11-02 |
| 6812076 | Dual silicon layer for chemical mechanical polishing planarization | Krishnashree Achuthan, Shibly S. Ahmed, Bin Yu | 2004-11-02 |
| 6803631 | Strained channel finfet | Srikanteswara Dakshina-Murthy, Judy Xilin An, Zoran Krivokapic, Bin Yu | 2004-10-12 |
| 6800910 | FinFET device incorporating strained silicon in the channel region | Ming-Ren Lin, Jung-Suk Goo, Qi Xiang | 2004-10-05 |
| 6787406 | Systems and methods for forming dense n-channel and p-channel fins using shadow implanting | Wiley Eugene Hill, Shibly S. Ahmed, Bin Yu | 2004-09-07 |
| 6787864 | Mosfets incorporating nickel germanosilicided gate and methods for their formation | Eric N. Paton, Qi Xiang, Paul R. Besser, Ming-Ren Lin, Minh Van Ngo | 2004-09-07 |
| 6787854 | Method for forming a fin in a finFET device | Chih-Yuh Yang, Shibly S. Ahmed, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Bin Yu | 2004-09-07 |
| 6787439 | Method using planarizing gate material to improve gate critical dimension in semiconductor devices | Shibly S. Ahmed, Cyrus E. Tabery, Bin Yu | 2004-09-07 |
| 6764884 | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device | Bin Yu | 2004-07-20 |
| 6762483 | Narrow fin FinFET | Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina-Murthy, Bin Yu | 2004-07-13 |
| 6762448 | FinFET device with multiple fin structures | Ming-Ren Lin, Bin Yu | 2004-07-13 |
| 6756276 | Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication | Qi Xiang, Jung-Suk Goo | 2004-06-29 |
| 6756643 | Dual silicon layer for chemical mechanical polishing planarization | Krishnashree Achuthan, Shibly S. Ahmed, Bin Yu | 2004-06-29 |
| 6730576 | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer | Paul R. Besser, Jung-Suk Goo, Minh Van Ngo, Eric N. Paton, Qi Xiang | 2004-05-04 |
| 6716690 | Uniformly doped source/drain junction in a double-gate MOSFET | Judy Xilin An, Bin Yu | 2004-04-06 |
| 6709982 | Double spacer FinFET formation | Matthew S. Buynoski, Judy Xilin An, Bin Yu | 2004-03-23 |
| 6706571 | Method for forming multiple structures in a semiconductor device | Bin Yu, Judy Xilin An, Cyrus E. Tabery | 2004-03-16 |
| 6703648 | Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication | Qi Xiang, Eric N. Paton | 2004-03-09 |
| 6686231 | Damascene gate process with sacrificial oxide in semiconductor devices | Shibly S. Ahmed, Bin Yu | 2004-02-03 |
| 6680233 | Semiconductor device formed with disposable spacer and liner using high-K material and method of fabrication | Bin Yu, Qi Xiang | 2004-01-20 |