Issued Patents 2004
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6815233 | Method of simultaneous display of die and wafer characterization in integrated circuit technology development | Shivananda Shetty | 2004-11-09 |
| 6770523 | Method for semiconductor wafer planarization by CMP stop layer formation | Kashmir Sahota, Arvind Halliyal, Minh Van Ngo, Krishnashree Achuthan | 2004-08-03 |
| 6766265 | Processing tester information by trellising in integrated circuit technology development | Shivananda Shetty | 2004-07-20 |
| 6759179 | Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process | Khoi A. Phan, Jerry Cheng, Richard Bartlett, Anthony P. Coniglio, Wolfram Grundke +3 more | 2004-07-06 |
| 6723605 | Method for manufacturing memory with high conductivity bitline and shallow trench isolation integration | Kashmir Sahota | 2004-04-20 |