Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12002687 | System and methods for wafer drying | Antonio Luis Pacheco Rotondaro, Derek Bassett, Hitoshi Kosugi | 2024-06-04 |
| 11515178 | System and methods for wafer drying | Antonio Luis Pacheco Rotondaro, Derek Bassett, Hitoshi Kosugi | 2022-11-29 |
| 11376640 | Apparatus and method to electrostatically remove foreign matter from substrate surfaces | Antonio Luis Pacheco Rotondaro, Derek Bassett, Ihsan Simms | 2022-07-05 |
| 10886290 | Etching of silicon nitride and silica deposition control in 3D NAND structures | Derek Bassett, Antonio Luis Pacheco Rotondaro, Ihsan Simms | 2021-01-05 |
| 10844332 | Aqueous cleaning solution and method of protecting features on a substrate during etch residue removal | Takayuki Toshima, Hiroshi Marumoto, Yoshinori Nishiwaki | 2020-11-24 |
| 8049254 | Semiconductor device with gate-undercutting recessed region | Antonio Luis Pacheco Rotondaro, Elisabeth Marley Koontz | 2011-11-01 |
| 7732345 | Method for using a modified post-etch clean rinsing agent | Phillip D. Matz | 2010-06-08 |
| 7528072 | Crystallographic preferential etch to define a recessed-region for epitaxial growth | Antonio Luis Pacheco Rotondaro, Elisabeth Marley Koontz | 2009-05-05 |
| 7422969 | Multi-step process for patterning a metal gate electrode | Antonio Luis Pacheco Rotondaro, Deborah J. Riley | 2008-09-09 |
| 7371691 | Silicon recess improvement through improved post implant resist removal and cleans | Lindsey Hall, Deborah J. Riley | 2008-05-13 |
| 7323403 | Multi-step process for patterning a metal gate electrode | Antonio Luis Pacheco Rotondaro, Deborah J. Riley | 2008-01-29 |
| 7195679 | Versatile system for wafer edge remediation | Changfeng Xia | 2007-03-27 |
| 7132365 | Treatment of silicon prior to nickel silicide formation | Sue Crank, Shirin Siddiqui, Deborah J. Riley, Peijun Chen | 2006-11-07 |
| 7037823 | Method to reduce silanol and improve barrier properties in low k dielectric ic interconnects | Phillip D. Matz, Sameer Ajmera, Changming Jin | 2006-05-02 |
| 6995088 | Surface treatment of copper to improve interconnect formation | Sanjeev Aggarwal, Lindsey Hall | 2006-02-07 |
| 6787425 | Methods for fabricating transistor gate structures | Antonio Luis Pacheco Rotondaro, Stephanie W. Butler, Majid Mansoori | 2004-09-07 |
| 6709875 | Contamination control for embedded ferroelectric device fabrication processes | Stephen Roy Gilbert, Laura Wills Mirkarimi, Scott R. Summerfelt, Luigi Colombo | 2004-03-23 |