Issued Patents All Time
Showing 101–125 of 136 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10090253 | Semiconductor package | Jing-Cheng Lin, Po-Hao Tsai, Szu-Wei Lu | 2018-10-02 |
| 10049928 | Embedded 3D interposer structure | Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu | 2018-08-14 |
| 10032662 | Packaged semiconductor devices and packaging methods thereof | Shu-Hang Liao, Szu-Wei Lu, Jing-Cheng Lin | 2018-07-24 |
| 9929109 | Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure | Chih-Wei Wu, Szu-Wei Lu, Jing-Cheng Lin | 2018-03-27 |
| 9895871 | De-bonding and cleaning process and system | Jing-Cheng Lin, Szu-Wei Lu | 2018-02-20 |
| 9818697 | Semiconductor package manufacturing method | Jing-Cheng Lin, Po-Hao Tsai, Szu-Wei Lu | 2017-11-14 |
| 9773755 | Substrate interconnections having different sizes | Wen-Wei Shen, Chen-Shien Chen, Ming-Fa Chen | 2017-09-26 |
| 9773724 | Semiconductor devices, methods of manufacture thereof, and semiconductor device packages | I-Ting Chen, Po-Hao Tsai, Szu-Wei Lu, Jing-Cheng Lin | 2017-09-26 |
| 9704825 | Chip packages and methods of manufacture thereof | Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu | 2017-07-11 |
| 9662872 | De-bonding and cleaning process and system | Jing-Cheng Lin, Szu-Wei Lu | 2017-05-30 |
| 9570421 | Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure | Chih-Wei Wu, Szu-Wei Lu, Jing-Cheng Lin | 2017-02-14 |
| 9508666 | Packaging structures and methods with a metal pillar | Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Kuo-Ching Hsu, Cheng-Chieh Hsieh +3 more | 2016-11-29 |
| 9475272 | De-bonding and cleaning process and system | Jing-Cheng Lin, Szu-Wei Lu | 2016-10-25 |
| 9472516 | Fan out package structure and methods of forming | Pu Wang, Szu-Wei Lu, Jing-Cheng Lin | 2016-10-18 |
| 9406588 | Semiconductor package and manufacturing method thereof | Jing-Cheng Lin, Po-Hao Tsai, Szu-Wei Lu | 2016-08-02 |
| 9406500 | Flux residue cleaning system and method | I-Ting Chen, Szu-Wei Lu, Jing-Cheng Lin | 2016-08-02 |
| 9349701 | Self-aligning conductive bump structure and method of fabrication | Cheng-Lin Huang, I-Ting Chen, Po-Hao Tsai, Szu-Wei Lu, Jing-Cheng Lin +2 more | 2016-05-24 |
| 9343431 | Dam structure for enhancing joint yield in bonding processes | Szu-Wei Lu, Jing-Cheng Lin | 2016-05-17 |
| 9209045 | Fan out package structure and methods of forming | Pu Wang, Szu-Wei Lu, Jing-Cheng Lin | 2015-12-08 |
| 9142533 | Substrate interconnections having different sizes | Wen-Wei Shen, Chen-Shien Chen, Ming-Fa Chen | 2015-09-22 |
| 9024438 | Self-aligning conductive bump structure and method of making the same | Cheng-Lin Huang, I-Ting Chen, Po-Hao Tsai, Szu-Wei Lu, Jing-Cheng Lin +2 more | 2015-05-05 |
| 8994155 | Packaging devices, methods of manufacture thereof, and packaging methods | Tsung-Fu Tsai, Yu-Chang Lin, Wei Wu, Yian-Liang Kuo, Chia-Wei Tu | 2015-03-31 |
| 8963334 | Die-to-die gap control for semiconductor structure and method | Jing-Cheng Lin, Szu-Wei Lu, Ying-Da Wang, Li-Chung Kuo, Long Hua Lee +2 more | 2015-02-24 |
| 8901735 | Connector design for packaging integrated circuits | Chen-Hua Yu, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Cheng-Chieh Hsieh +4 more | 2014-12-02 |
| 8871568 | Packages and method of forming the same | Szu-Wei Lu, Jing-Cheng Lin | 2014-10-28 |