Issued Patents All Time
Showing 76–100 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8887106 | Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process | Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao | 2014-11-11 |
| 8856696 | Integrated circuit layout modification | Wen-Hao Chen, Yuan-Te Hou | 2014-10-07 |
| 8856701 | Method of radio-frequency and microwave device generation | Chin-Sheng Chen, Tsun-Yu Yang, Wei Hu, Tao Wen Chung, Hui Yu Lee +1 more | 2014-10-07 |
| 8850368 | Double patterning technology (DPT) layout routing | Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang | 2014-09-30 |
| 8826213 | Parasitic capacitance extraction for FinFETs | Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao, Ze-Ming Wu, Hsien-Hsin Sean Lee | 2014-09-02 |
| 8813016 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang +2 more | 2014-08-19 |
| 8775977 | Decomposition and marking of semiconductor device design layout in double patterning lithography | Chin-Chang Hsu, Wen-Ju Yang, Hsiao-Shu Chao, Lee-Chung Lu | 2014-07-08 |
| 8751975 | RC corner solutions for double patterning technology | Ke-Ying Su, Hsiao-Shu Chao | 2014-06-10 |
| 8732628 | Method and system for photomask assignment for double patterning technology | Meng-Fan Wu, I-Fan Lin, Ke-Ying Su, Hsiao-Shu Chao | 2014-05-20 |
| 8707230 | Method and system for semiconductor simulation | Wei Hu, Chin-Cheng Kuo, Cheng-Hung Yeh, Jui-Feng Kuan | 2014-04-22 |
| 8707245 | Semiconductor device design method, system and computer-readable medium | Ching-Shun Yang, Ze-Ming Wu, Hsiao-Shu Chao | 2014-04-22 |
| 8694938 | Discrete device modeling | Ching-Shun Yang, Chih-Ming Yang, Wei Hu | 2014-04-08 |
| 8671382 | Method of generating RC technology file | Ke-Ying Su, Hsiao-Shu Chao, Yung-Chin Hou | 2014-03-11 |
| 8645877 | Multi-patterning method | Chin-Chang Hsu, Ying-Yu Shen, Wen-Ju Yang, Hsiao-Shu Chao | 2014-02-04 |
| 8631366 | Integrated circuit design using DFM-enhanced architecture | Yung-Chin Hou, Lee-Chung Lu, Li-Chun Tien, Chun-Hui Tai, Ta-Pen Guo +1 more | 2014-01-14 |
| 8621409 | System and method for reducing layout-dependent effects | Hui Yu Lee, Feng-Wei Kuo, Ching-Shun Yang, Jui-Feng Kuan | 2013-12-31 |
| 8612912 | Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment | Wen-Hao Chen | 2013-12-17 |
| 8601416 | Method of circuit design yield analysis | Chin-Cheng Kuo, Wei Hu, Jui-Feng Kuan | 2013-12-03 |
| 8601408 | Method and system for replacing a pattern in a layout | Huang-Yu Chen, Yuan-Te Hou, Chung-Min Fu, Chung-Hsing Wang, Wen-Hao Chen | 2013-12-03 |
| 8495532 | Systems and methods for creating frequency-dependent RC extraction netlist | Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao | 2013-07-23 |
| 8473873 | Multi-patterning method | Chin-Chang Hsu, Ying-Yu Shen, Wen-Ju Yang, Hsiao-Shu Chao | 2013-06-25 |
| 8468470 | Multi-patterning method | Chin-Chang Hsu, Wen-Ju Yang, Hsiao-Shu Chao | 2013-06-18 |
| 8453095 | Systems and methods for creating frequency-dependent netlist | Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Huang-Yu Chen +1 more | 2013-05-28 |
| 8448120 | RC extraction for single patterning spacer technique | Cheng-I Huang, Hsiao-Shu Chao | 2013-05-21 |
| 8448100 | Tool and method for eliminating multi-patterning conflicts | Hung-Lung Lin, Chin-Chang Hsu, Ying-Yu Shen, Wen-Ju Yang, Hsiao-Shu Chao +5 more | 2013-05-21 |