Issued Patents All Time
Showing 101–120 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8434043 | Methodology for analysis and fixing guidance of pre-coloring layout | Chin-Chang Hsu, HungLung Lin, Wen-Ju Yang, Hsiao-Shu Chao | 2013-04-30 |
| 8418098 | Advisory system for verifying sensitive circuits in chip-design | Chi-Heng Huang, Gary Lin, Chu Fu Chen, Fu-Lung Hsueh | 2013-04-09 |
| 8418117 | Chip-level ECO shrink | Huang-Yu Chen, Ho Che Yu, Chung-Hsing Wang, Hsiao-Shu Chao, Lee-Chung Lu | 2013-04-09 |
| 8418112 | Method of generating RC technology file | Ke-Ying Su, Hsiao-Shu Chao, Yung-Chin Hou | 2013-04-09 |
| 8336002 | IC design flow enhancement with CMP simulation | Gwan Sin Chang, Ivy Chiu, Ke-Ying Su | 2012-12-18 |
| 8327301 | Routing method for double patterning design | Lee-Chung Lu, Ru-Gun Liu, Chih-Ming Lai | 2012-12-04 |
| 8286119 | Systematic method for variable layout shrink | Fu-Chieh Hsu, Louis Liu, Lee-Chung Lu | 2012-10-09 |
| 8255837 | Methods for cell boundary isolation in double patterning design | Lee-Chung Lu, Yuan-Te Hou, Yung-Chin Hou, Li-Chun Tien | 2012-08-28 |
| 8252489 | Mask-shift-aware RC extraction for double patterning design | Ke-Ying Su, Chung-Hsing Wang, Jui-Feng Kuan, Hsiao-Shu Chao | 2012-08-28 |
| 8245174 | Double patterning friendly lithography method and system | Ru-Gun Liu, Lee-Chung Lu | 2012-08-14 |
| 8239806 | Routing system and method for double patterning technology | Huang-Yu Chen, Yuan-Te Hou, Gwan Sin Chang, Wen-Ju Yang, Zhe-Wei Jiang +1 more | 2012-08-07 |
| 8214773 | Methods for E-beam direct write lithography | Lee-Chung Lu, Ru-Gun Liu, Chih-Ming Lai | 2012-07-03 |
| 8201111 | Table-based DFM for accurate post-layout analysis | Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Chung-Kai Lin +5 more | 2012-06-12 |
| 8136168 | System and method for design-for-manufacturability data encryption | Gwan Sin Chang, Jill Liu, Hsiao-Shu Chiao | 2012-03-13 |
| 8119310 | Mask-shift-aware RC extraction for double patterning design | Lee-Chung Lu, Hsiao-Shu Chao, Ke-Ying Su, Cheng-Hung Yeh, Dian-Hau Chen +2 more | 2012-02-21 |
| 8037575 | Method for shape and timing equivalent dimension extraction | Ying-Chou Cheng, Chih-Ming Lai, Ru-Gun Liu, Tsong-Hua Ou, Min-Hong Wu +4 more | 2011-10-18 |
| 8001494 | Table-based DFM for accurate post-layout analysis | Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Chung-Kai Lin +5 more | 2011-08-16 |
| 7801717 | Method for smart dummy insertion to reduce run time and dummy count | Gwan Sin Chang, Cliff Hou | 2010-09-21 |
| 7725861 | Method, apparatus, and system for LPC hot spot fix | Chih-Ming Lai, Ru-Gun Liu | 2010-05-25 |
| 7467365 | Sanity checker for integrated circuits | George H. Chang, Chen-Teng Fan, Chen-Lin Yang, Yung-Chin Hou, Chu-Ping Wang | 2008-12-16 |