Issued Patents All Time
Showing 51–75 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9748228 | Structure and method for cooling three-dimensional integrated circuits | Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan | 2017-08-29 |
| 9698099 | Semiconductor structure having a plurality of conductive paths | Hui Yu Lee, Feng-Wei Kuo, Jui-Feng Kuan | 2017-07-04 |
| 9672315 | Optimization for circuit migration | Lee-Chung Lu, Chung-Hsing Wang, Chen-Fu Huang, Hsiao-Shu Chao, Chin-Yu Chiang +3 more | 2017-06-06 |
| 9367654 | Variation modeling | Chi-Wen Chang, Hui Yu Lee, Jui-Feng Kuan, Chin-Hua Wen, Wen-Shen Chou | 2016-06-14 |
| 9361425 | Method and apparatus for modeling multi-terminal MOS device for LVS and PDK | Chau-Wen Wei, Cheng-Te Chang, Chin-Yuan Huang, Chih-Ming Yang | 2016-06-07 |
| 9361423 | RC corner solutions for double patterning technology | Ke-Ying Su, Hsiao-Shu Chao | 2016-06-07 |
| 9355205 | Method and apparatus of a three dimensional integrated circuit | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan | 2016-05-31 |
| 9348965 | Parasitic component library and method for efficient circuit design and simulation using the same | Chin-Sheng Chen, Tsun-Yu Yang, Wei Hu, Tao Wen Chung, Jui-Feng Kuan | 2016-05-24 |
| 9335624 | Multi-patterning system and method using pre-coloring or locked patterns | Hui Yu Lee, Chi-Wen Chang, Chih-Ming Yang, Ya Yun Liu | 2016-05-10 |
| 9317650 | Double patterning technology (DPT) layout routing | Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang | 2016-04-19 |
| 9275186 | Optimization for circuit migration | Lee-Chung Lu, Chung-Hsing Wang, Chen-Fu Huang, Hsiao-Shu Chao, Chin-Yu Chiang +3 more | 2016-03-01 |
| 9262558 | RC extraction for single patterning spacer technique | Cheng-I Huang, Hsiao-Shu Chao | 2016-02-16 |
| 9230052 | Method of generating a simulation model of a predefined fabrication process | Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao | 2016-01-05 |
| 9213795 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang +2 more | 2015-12-15 |
| 9213797 | Method, system and computer program product for designing semiconductor device | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan | 2015-12-15 |
| 9129082 | Variation factor assignment | Chi-Wen Chang, Hui Yu Lee, Jui-Feng Kuan, Chin-Hua Wen, Wen-Shen Chou | 2015-09-08 |
| 9122833 | Method of designing fin field effect transistor (FinFET)-based circuit and system for implementing the same | Chin-Sheng Chen, Tsun-Yu Yang, Wei Hu, Jui-Feng Kuan, Ching-Shun Yang | 2015-09-01 |
| 9053255 | Semiconductor structure and method of generating masks for making integrated circuit | Hui Yu Lee, Feng-Wei Kuo, Jui-Feng Kuan | 2015-06-09 |
| 9026971 | Multi-patterning conflict free integrated circuit design | Chien Lin Ho, Chin-Chang Hsu, Hung-Lung Lin, Wen-Ju Yang, Tsong-Hua Ou +5 more | 2015-05-05 |
| 9000524 | Method and apparatus for modeling multi-terminal MOS device for LVS and PDK | Chau-Wen Wei, Cheng-Te Chang, Chin-Yuan Huang, Chih-Ming Yang | 2015-04-07 |
| 8977991 | Method and system for replacing a pattern in a layout | Huang-Yu Chen, Yuan-Te Hou, Chung-Min Fu, Chung-Hsing Wang, Wen-Hao Chen | 2015-03-10 |
| 8972919 | Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment | Wen-Hao Chen | 2015-03-03 |
| 8907441 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang +2 more | 2014-12-09 |
| 8904337 | Semiconductor device design method, system and computer-readable medium | Ching-Shun Yang, Ze-Ming Wu, Hsiao-Chu Chao | 2014-12-02 |
| 8893066 | Parasitic component library and method for efficient circuit design and simulation using the same | Chin-Sheng Chen, Tsun-Yu Yang, Wei Hu, Tao Wen Chung, Jui-Feng Kuan | 2014-11-18 |