Issued Patents All Time
Showing 26–50 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11282829 | Integrated circuit with mixed row heights | Kam-Tou Sio, Jiann-Tyng Tzeng, Chung-Hsing Wang | 2022-03-22 |
| 11182533 | Standard cells and variations thereof within a standard cell library | Sheng-Hsiung Chen, Jerry Chang Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang +2 more | 2021-11-23 |
| 11170150 | Method for making a semiconductor device | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan | 2021-11-09 |
| 11157677 | Merged pillar structures and method of generating layout diagram of same | Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang | 2021-10-26 |
| 11138360 | Semiconductor device with filler cell region, method of generating layout diagram and system for same | Po-Hsiang Huang, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Hui-Zhong Zhuang +2 more | 2021-10-05 |
| 11088084 | Electromagnetic shielding metal-insulator-metal capacitor structure | Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang +1 more | 2021-08-10 |
| 11030372 | Method for generating layout diagram including cell having pin patterns and semiconductor device based on same | Pin-Dai Sue, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu +4 more | 2021-06-08 |
| 10949597 | Through-silicon vias in integrated circuit packaging | Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Po-Hsiang Huang +2 more | 2021-03-16 |
| 10943729 | Entangled inductor structures | Ka Fai Chang, Chin-Chou Liu, Fong-Yuan Chang, Hui Yu Lee | 2021-03-09 |
| 10910365 | Structure and method for cooling three-dimensional integrated circuits | Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan | 2021-02-02 |
| 10811316 | Method and system of forming integrated circuit | Ka Fai Chang, Fong-Yuan Chang, Chin-Chou Liu | 2020-10-20 |
| 10763253 | Structure and method for cooling three-dimensional integrated circuits | Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan | 2020-09-01 |
| 10741539 | Standard cells and variations thereof within a standard cell library | Sheng-Hsiung Chen, Jerry Chang Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang +2 more | 2020-08-11 |
| 10678990 | Techniques based on electromigration characteristics of cell interconnect | Kuo-Nan Yang, Chung-Hsing Wang, Kumar Lalgudi | 2020-06-09 |
| 10665550 | Electromagnetic shielding metal-insulator-metal capacitor structure | Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang +1 more | 2020-05-26 |
| 10540475 | System for manufacturing a semiconductor device | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan | 2020-01-21 |
| 10515178 | Merged pillar structures and method of generating layout diagram of same | Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang | 2019-12-24 |
| 10396063 | Circuit with combined cells and method for manufacturing the same | Fong-Yuan Chang, Lee-Chung Lu, Sheng-Hsiung Chen, Po-Hsiang Huang, Shun Li Chen +4 more | 2019-08-27 |
| 10163787 | Semiconductor structure | Hui Yu Lee, Feng-Wei Kuo, Jui-Feng Kuan | 2018-12-25 |
| 10157254 | Techniques based on electromigration characteristics of cell interconnect | Kuo-Nan Yang, Chung-Hsing Wang, Kumar Lalgudi | 2018-12-18 |
| 10157252 | Method and apparatus of a three dimensional integrated circuit | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan | 2018-12-18 |
| 10095827 | Method of manufacturing a semiconductor device | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan | 2018-10-09 |
| 9984196 | Method and apparatus for modeling multi-terminal MOS device for LVS and PDK | Chau-Wen Wei, Cheng-Te Chang, Chin-Yuan Huang, Chih-Ming Yang | 2018-05-29 |
| 9934352 | Method and system for manufacturing a semiconductor device | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan | 2018-04-03 |
| 9748228 | Structure and method for cooling three-dimensional integrated circuits | Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan | 2017-08-29 |