Issued Patents All Time
Showing 201–225 of 229 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9190348 | Scheme for connector site spacing and resulting structures | Yu-Feng Chen, Yen-Liang Lin, Sheng-Yu Wu, Chen-Shien Chen | 2015-11-17 |
| 9165796 | Methods and apparatus for bump-on-trace chip packaging | Yen-Liang Lin, Chang-Chia Huang, Sheng-Yu Wu, Chen-Shien Chen | 2015-10-20 |
| 9153550 | Substrate design with balanced metal and solder resist density | Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Chen-Shien Chen | 2015-10-06 |
| 9111817 | Bump structure and method of forming same | Guan-Yu Chen, Yu-Wei Lin, Yu-Jen Tseng, Chen-Shien Chen | 2015-08-18 |
| 9105530 | Conductive contacts having varying widths and method of manufacturing same | Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Chen-Shien Chen | 2015-08-11 |
| 9105533 | Bump structure having a single side recess | Chih-Horng Chang, Chen-Shien Chen, Yen-Liang Lin | 2015-08-11 |
| 9093332 | Elongated bump structure for semiconductor devices | Yu-Feng Chen, Chen-Shien Chen, Chen-Hua Yu, Sheng-Yu Wu, Chita Chuang | 2015-07-28 |
| 9048333 | Isolation rings for packages and the method of forming the same | Chih-Horng Chang, Tsung-Fu Tsai, Min-Feng Ku | 2015-06-02 |
| 9041223 | Bump-on-trace (BOT) structures | Yuh Chern Shieh, Han-Ping Pu, Yu-Feng Chen | 2015-05-26 |
| 9006909 | Solder mask shape for BOT laminate packages | Chih-Horng Chang, Sheng-Yu Wu, Pei-Chun Tsai, Chen-Shien Chen | 2015-04-14 |
| 8981576 | Structure and method for bump to landing trace ratio | Chen-Hua Yu, Chen-Shien Chen, Mirng-Ji Lii, Sheng-Yu Wu, Yen-Liang Lin | 2015-03-17 |
| 8970033 | Extending metal traces in bump-on-trace structures | Yu-Feng Chen, Yuh Chern Shieh, Tsung-Shu Lin, Han-Ping Pu, Jiun Yi Wu | 2015-03-03 |
| 8922006 | Elongated bumps in integrated circuit devices | Yen-Liang Lin, Chen-Shien Chen, Sheng-Yu Wu, Tsung-Shu Lin, Chang-Chia Huang | 2014-12-30 |
| 8921222 | Pillar structure having a non-planar surface for semiconductor devices | Chen-Shien Chen, Ching-Wen Hsiao | 2014-12-30 |
| 8922005 | Methods and apparatus for package on package devices with reversed stud bump through via interconnections | Yen-Chang Hu, Ching-Wen Hsiao, Chih-Hua Chen, Chen-Shien Chen | 2014-12-30 |
| 8912649 | Dummy flip chip bumps for reducing stress | Sheng-Yu Wu, Chita Chuang, Chen-Shien Chen | 2014-12-16 |
| 8907479 | Treating copper surfaces for packaging | Chih-Horng Chang | 2014-12-09 |
| 8853853 | Bump structures | Chih-Horng Chang, Chen-Shien Chen, Yen-Liang Lin | 2014-10-07 |
| 8823170 | Apparatus and method for three dimensional integrated circuits | Sheng-Yu Wu, Pei-Chun Tsai, Chih-Horng Chang, Chen-Shien Chen | 2014-09-02 |
| 8803319 | Pillar structure having a non-planar surface for semiconductor devices | Chen-Shien Chen, Ching-Wen Hsiao | 2014-08-12 |
| 8710681 | Isolation rings for blocking the interface between package components and the respective molding compound | Chih-Horng Chang, Tsung-Fu Tsai, Min-Feng Ku | 2014-04-29 |
| 8664041 | Method for designing a package and substrate layout | Yu-Jen Tseng, Guan-Yu Chen, Sheng-Yu Wu, Chen-Hua Yu, Mirng-Ji Lii +1 more | 2014-03-04 |
| 8643196 | Structure and method for bump to landing trace ratio | Chen-Hua Yu, Chen-Shien Chen, Mirng-Ji Lii, Sheng-Yu Wu, Yen-Liang Lin | 2014-02-04 |
| 8623756 | Reflow system and method for conductive connections | Chita Chuang, Sheng-Yu Wu, Pei-Chun Tsai, Ming-Da Cheng, Chen-Shien Chen | 2014-01-07 |
| 8598691 | Semiconductor devices and methods of manufacturing and packaging thereof | Sheng-Yu Wu, Chen-Shien Chen, Ming-Da Cheng | 2013-12-03 |