Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9935073 | Semiconductor structure and manufacturing method of the same | Yen-Liang Lin, Mirng-Ji Lii, Tin-Hao Kuo, Chen-Shien Chen, Yu-Feng Chen | 2018-04-03 |
| 9871013 | Contact area design for solder bonding | Pei-Chun Tsai, Yu-Feng Chen, Tin-Hao Kuo, Chen-Shien Chen, Yu-Chih Huang | 2018-01-16 |
| 9711477 | Dummy flip chip bumps for reducing stress | Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen | 2017-07-18 |
| 9679862 | Semiconductor device having conductive bumps of varying heights | Yen-Liang Lin, Tin-Hao Kuo, Chen-Shien Chen | 2017-06-13 |
| 9646943 | Connector structure and method of forming same | Chen-Shien Chen, Mirng-Ji Lii, Chita Chuang | 2017-05-09 |
| 9633965 | Semiconductor structure and manufacturing method of the same | Yen-Liang Lin, Mirng-Ji Lii, Tin-Hao Kuo, Chen-Shien Chen, Yu-Feng Chen | 2017-04-25 |
| 9583367 | Methods and apparatus for bump-on-trace chip packaging | Chang-Chia Huang, Chen-Shien Chen, Tin-Hao Kuo, Yen-Liang Lin | 2017-02-28 |
| 9559069 | Semiconductor device, integrated circuit structure using the same, and manufacturing method thereof | Yu-Feng Chen, Chen-Shien Chen, Tin-Hao Kuo, Yen-Liang Lin | 2017-01-31 |
| 9496233 | Interconnection structure and method of forming same | Yu-Wei Lin, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen | 2016-11-15 |
| 9484317 | Scheme for connector site spacing and resulting structures | Yu-Feng Chen, Yen-Liang Lin, Tin-Hao Kuo, Chen-Shien Chen | 2016-11-01 |
| 9449941 | Connecting function chips to a package to form package-on-package | Pei-Chun Tsai, Ching-Wen Hsiao, Tin-Hao Kuo, Chen-Shien Chen, Chung-Shi Liu +2 more | 2016-09-20 |
| 9425136 | Conical-shaped or tier-shaped pillar connections | Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Yao-Chun Chuang | 2016-08-23 |
| 9287234 | Dummy flip chip bumps for reducing stress | Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen | 2016-03-15 |
| 9269688 | Bump-on-trace design for enlarge bump-to-trace distance | Tin-Hao Kuo, Chen-Shien Chen | 2016-02-23 |
| 9190348 | Scheme for connector site spacing and resulting structures | Yu-Feng Chen, Yen-Liang Lin, Tin-Hao Kuo, Chen-Shien Chen | 2015-11-17 |
| 9165796 | Methods and apparatus for bump-on-trace chip packaging | Yen-Liang Lin, Chang-Chia Huang, Tin-Hao Kuo, Chen-Shien Chen | 2015-10-20 |
| 9093332 | Elongated bump structure for semiconductor devices | Tin-Hao Kuo, Yu-Feng Chen, Chen-Shien Chen, Chen-Hua Yu, Chita Chuang | 2015-07-28 |
| 9006909 | Solder mask shape for BOT laminate packages | Chih-Horng Chang, Pei-Chun Tsai, Tin-Hao Kuo, Chen-Shien Chen | 2015-04-14 |
| 8981576 | Structure and method for bump to landing trace ratio | Chen-Hua Yu, Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Yen-Liang Lin | 2015-03-17 |
| 8927391 | Package-on-package process for applying molding compound | Meng-Tse Chen, Wei-Hung Lin, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Peng Tsai +6 more | 2015-01-06 |
| 8922006 | Elongated bumps in integrated circuit devices | Yen-Liang Lin, Chen-Shien Chen, Tin-Hao Kuo, Tsung-Shu Lin, Chang-Chia Huang | 2014-12-30 |
| 8912649 | Dummy flip chip bumps for reducing stress | Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen | 2014-12-16 |
| 8823170 | Apparatus and method for three dimensional integrated circuits | Pei-Chun Tsai, Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen | 2014-09-02 |
| 8664041 | Method for designing a package and substrate layout | Yu-Jen Tseng, Guan-Yu Chen, Chen-Hua Yu, Mirng-Ji Lii, Chen-Shien Chen +1 more | 2014-03-04 |
| 8643196 | Structure and method for bump to landing trace ratio | Chen-Hua Yu, Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Yen-Liang Lin | 2014-02-04 |