Issued Patents All Time
Showing 51–75 of 111 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9412649 | Method of fabricating semiconductor device | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2016-08-09 |
| 9366969 | Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication | Chia-Chu Liu, Norman Chen, Vencent Chang, Chin-Hsiang Lin | 2016-06-14 |
| 9281205 | Method for etching an ultra thin film | Chia-Chu Liu, Shang-Wern Chang, Chih-Yang Yeh | 2016-03-08 |
| 9274414 | Method for making a lithography mask | Yu-Lun Liu, Chia-Chu Liu, Chung-Ming Wang, Chie-Chieh Lin | 2016-03-01 |
| 9184101 | Method for removing semiconductor fins using alternating masks | Tzu-Chun Lo, Min Cheng, Hsiao-Wei Su, Jeng-Shiun Ho, Ching-Che Tsai +3 more | 2015-11-10 |
| 9129974 | Enhanced FinFET process overlay mark | Chi-Wen Hsieh, Chi-Kang Chang, Chia-Chu Liu, Meng-Wei Chen | 2015-09-08 |
| 9091923 | Contrast enhancing exposure system and method for use in semiconductor fabrication | George Liu, Vencent Chang, Norman Chen, Chin-Hsiang Lin | 2015-07-28 |
| 9070623 | Controlling gate formation for high density cell layout | Harry-Hak-Lay Chuang, Bao-Ru Young, Cheng-Cheng Kuo, George Liu, Tsung-Chieh Tsai +1 more | 2015-06-30 |
| 9059001 | Semiconductor device with biased feature | Chia-Chu Liu, Minchang Liang, Mu-Chi Chiang | 2015-06-16 |
| 9026957 | Method of defining an intensity selective exposure photomask | Chia-Chu Liu, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng +9 more | 2015-05-05 |
| 8969922 | Field effect transistors and method of forming the same | Chia-Chu Liu, Mu-Chi Chiang, Yao-Kwang Wu, Bi-Fen Wu, Huan-Just Lin +2 more | 2015-03-03 |
| 8932936 | Method of forming a FinFET device | Chia-Chu Liu, Chih-Hsiung Peng, Chi-Kang Chang, Chiang Mu-Chi, Sheng-Yu Chang +3 more | 2015-01-13 |
| 8906595 | Method for improving resist pattern peeling | Yu-Lun Liu, Chia-Chu Liu, Chung-Ming Wang, Chie-Chieh Lin | 2014-12-09 |
| 8877598 | Method of lithography process with an under isolation material layer | Chung-Ming Wang, Yu-Lun Liu, Chia-Chu Liu, Ya Hui Chang | 2014-11-04 |
| 8872339 | Semiconductors structure with elements having different widths and methods of making the same | Chia-Chu Liu, Yi-Shien Mor, Yu-Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh | 2014-10-28 |
| 8850369 | Metal cut process flow | Yuan-Hsiang Lung, Meng-Wei Chen, Chia-Ying Lee | 2014-09-30 |
| 8846302 | Semiconductor structure and method and tool for forming the semiconductor structure | George Liu | 2014-09-30 |
| 8840796 | Integrated circuit method with triple patterning | Chia-Chu Liu, Meng-Wei Chen | 2014-09-23 |
| 8822343 | Enhanced FinFET process overlay mark | Chi-Wen Hsieh, Chi-Kang Chang, Chia-Chu Liu, Meng-Wei Chen | 2014-09-02 |
| 8815496 | Method for patterning a photosensitive layer | Hsiao-Tzu Lu, Tsiao-Chen Wu, Vencent Chang, George Liu | 2014-08-26 |
| 8765363 | Method of forming a resist pattern with multiple post exposure baking steps | Chung-Ming Wang, Yu-Lun Liu, Chia-Chu Liu | 2014-07-01 |
| 8735994 | Electrical-free dummy gate | Chia-Chu Liu, Chiang Mu-Chi | 2014-05-27 |
| 8732626 | System and method of circuit layout for multiple cells | Chia-Chu Liu | 2014-05-20 |
| 8716139 | Method of patterning a semiconductor device | George Liu, Meng-Wei Chen | 2014-05-06 |
| 8703392 | Method and apparatus for developing process | Yu-Lun Liu, Chia-Chu Liu, Chung-Ming Wang, Ying-Hao Su | 2014-04-22 |