Issued Patents All Time
Showing 26–50 of 159 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11814731 | Semiconductor tool having controllable ambient environment processing zones | Chiao-Chun Hsu, Chih-Ming Chen, Sheng-Hsun Lu | 2023-11-14 |
| 11784204 | Enhanced trench isolation structure | Min-Ying Tsai, Cheng-Te Lee, Rei-Lin Chu, Ching-I Li | 2023-10-10 |
| 11721752 | Semiconductor device having doped seed layer and method of manufacturing the same | Chi-Ming Chen, Po-Chun Liu, Chia-Shiung Tsai, Ru-Liang Lee | 2023-08-08 |
| 11713241 | Packaging method and associated packaging structure | Chih-Ming Chen, Yuan-Chih Hsieh | 2023-08-01 |
| 11688717 | Mechanical wafer alignment detection for bonding process | Ching-Hung Wang, Yeong-Jyh Lin, Ching-I Li, Tzu Wei Yu | 2023-06-27 |
| 11652058 | Substrate loss reduction for semiconductor devices | Xin-Hua Huang, Kuei-Ming Chen | 2023-05-16 |
| 11594606 | Method of implanting dopants into a group III-nitride structure and device formed | Han-Chin Chiu, Chi-Ming Chen, Chen-Hao Chiang | 2023-02-28 |
| 11594593 | Method to reduce breakdown failure in a MIM capacitor | Hsing-Lien Lin, Chii-Ming Wu, Chia-Shiung Tsai, Rei-Lin Chu | 2023-02-28 |
| 11594413 | Semiconductor structure having sets of III-V compound layers and method of forming | Chi-Ming Chen, Po-Chun Liu, Chia-Shiung Tsai | 2023-02-28 |
| 11551927 | High electron mobility transistor (HEMT) having an indium-containing layer and method of manufacturing the same | Po-Chun Liu, Chung-Chieh Hsu, Chi-Ming Chen, Chen-Hao Chiang, Min-Chang Ching | 2023-01-10 |
| 11527702 | Piezoelectric device with hydrogen getter | Chih-Ming Chen | 2022-12-13 |
| 11522049 | Diffusion barrier layer for source and drain structures to increase transistor performance | Kuei-Ming Chen, Chi-Ming Chen | 2022-12-06 |
| 11515408 | Rough buffer layer for group III-V devices on silicon | Kuei-Ming Chen, Chi-Ming Chen | 2022-11-29 |
| 11430729 | MIM capacitor with a symmetrical capacitor insulator structure | Hsing-Lien Lin, Cheng-Te Lee, Rei-Lin Chu, Chii-Ming Wu, Yeur-Luen Tu | 2022-08-30 |
| 11417520 | Semiconductor structure having sets of III-V compound layers and method of forming | Chi-Ming Chen, Po-Chun Liu, Chia-Shiung Tsai | 2022-08-16 |
| 11387748 | Self-aligned dielectric liner structure for protection in MEMS comb actuator | Chiao-Chun Hsu, Chih-Ming Chen, Lung Yuan Pan | 2022-07-12 |
| 11362038 | Photolithography alignment process for bonded wafers | Yeong-Jyh Lin, Ching-I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu +2 more | 2022-06-14 |
| 11329148 | Semiconductor device having doped seed layer and method of manufacturing the same | Chi-Ming Chen, Po-Chun Liu, Chia-Shiung Tsai, Ru-Liang Lee | 2022-05-10 |
| 11279615 | Method for manufacturing a MEMS device by first hybrid bonding a CMOS wafer to a MEMS wafer | Hung-Hua Lin, Chang-Ming Wu, Ping-Yin Liu, Jung-Huei Peng | 2022-03-22 |
| 11232946 | Method of optimizing film deposition process in semiconductor fabrication by using gas sensor | Rei-Lin Chu, Chih-Ming Chen, Yeur-Luen Tu | 2022-01-25 |
| 11222849 | Substrate loss reduction for semiconductor devices | Xin-Hua Huang, Kuei-Ming Chen | 2022-01-11 |
| 11211362 | 3D trench capacitor for integrated passive devices | Xin-Hua Huang, Yeong-Jyh Lin, Rei-Lin Chu | 2021-12-28 |
| 11164945 | SOI substrate, semiconductor device and method for manufacturing the same | Cheng-Ta Wu, Kuo-Hwa Tzeng, Chih-Hao Wang, Yeur-Luen Tu | 2021-11-02 |
| 11152455 | Method to reduce breakdown failure in a MIM capacitor | Hsing-Lien Lin, Chii-Ming Wu, Chia-Shiung Tsai, Rei-Lin Chu | 2021-10-19 |
| 11078075 | Packaging method and associated packaging structure | Chih-Ming Chen, Yuan-Chih Hsieh | 2021-08-03 |