Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12237165 | Method for wafer bonding including edge trimming | Yung-Lung Lin, Hau-Yi Hsiao, Chih-Hui Huang, Cheng-Hsien Chou | 2025-02-25 |
| 12211877 | Back-side deep trench isolation structure for image sensor | Cheng-Ta Wu, Yeur-Luen Tu | 2025-01-28 |
| 12027469 | Electronic device package and method of manufacturing the same | En Hao HSU, Chia-Pin Chen, Chi-Long Tsai | 2024-07-02 |
| 11955496 | Back-side deep trench isolation structure for image sensor | Cheng-Ta Wu, Yeur-Luen Tu | 2024-04-09 |
| 11855159 | Method for forming thin semiconductor-on-insulator (SOI) substrates | Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Shih Pei Chou, Yu-Hung Cheng +1 more | 2023-12-26 |
| 11264469 | Method for forming thin semiconductor-on-insulator (SOI) substrates | Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Shih Pei Chou, Yu-Hung Cheng +1 more | 2022-03-01 |
| 11164945 | SOI substrate, semiconductor device and method for manufacturing the same | Cheng-Ta Wu, Chih-Hao Wang, Yeur-Luen Tu, Chung-Yi Yu | 2021-11-02 |
| 11087971 | Method for manufacturing semiconductor device and manufacturing method of the same | Yung-Lung Lin, Hau-Yi Hsiao, Chih-Hui Huang, Cheng-Hsien Chou | 2021-08-10 |
| 11063117 | Semiconductor device structure having carrier-trapping layers with different grain sizes | Yu-Hung Cheng, Yong-En Syu, Ke-Dian Wu, Cheng-Ta Wu, Yeur-Luen Tu +2 more | 2021-07-13 |
| 10658474 | Method for forming thin semiconductor-on-insulator (SOI) substrates | Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Shih Pei Chou, Yu-Hung Cheng +1 more | 2020-05-19 |
| 10504716 | Method for manufacturing semiconductor device and manufacturing method of the same | Yung-Lung Lin, Hau-Yi Hsiao, Chih-Hui Huang, Cheng-Hsien Chou | 2019-12-10 |
| 10468486 | SOI substrate, semiconductor device and method for manufacturing the same | Cheng-Ta Wu, Chih-Hao Wang, Yeur-Luen Tu, Chung-Yi Yu | 2019-11-05 |
| 10204822 | Method for forming trench liner passivation | Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Yeur-Luen Tu | 2019-02-12 |
| 9917003 | Trench liner passivation for dark current improvement | Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Yeur-Luen Tu | 2018-03-13 |
| 9281331 | High dielectric constant structure for the vertical transfer gates of a complementary metal-oxide semiconductor (CMOS) image sensor | Sheng-Chau Chen, Chih-Yu Lai, Kuo-Ming Wu, Cheng-Hsien Chou, Cheng-Yuan Tsai +2 more | 2016-03-08 |
| 9245792 | Method for forming interconnect structures | Neng-Kuo Chen, Cheng-Yuan Tsai | 2016-01-26 |
| 9159808 | Selective etch-back process for semiconductor devices | Neng-Kuo Chen, Cheng-Yuan Tsai | 2015-10-13 |
| 8546242 | Hybrid gap-fill approach for STI formation | Neng-Kuo Chen, Chih-Hsiang Chang, Cheng-Yuan Tsai | 2013-10-01 |
| 8319311 | Hybrid STI gap-filling approach | Neng-Kuo Chen, Cheng-Yuan Tsai | 2012-11-27 |
| 8187948 | Hybrid gap-fill approach for STI formation | Neng-Kuo Chen, Chih-Hsiang Chang, Cheng-Yuan Tsai | 2012-05-29 |
| 8173516 | Method of forming shallow trench isolation structure | Neng-Kuo Chen, Cheng-Yuan Tsai | 2012-05-08 |
| 7892929 | Shallow trench isolation corner rounding | Neng-Kuo Chen, Cheng-Yuan Tsai, Jeffrey Junhao Xu | 2011-02-22 |
| 7655532 | STI film property using SOD post-treatment | Neng-Kuo Chen, Cheng-Yuan Tsai | 2010-02-02 |