Issued Patents All Time
Showing 51–75 of 159 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11047050 | Semiconductor tool having controllable ambient environment processing zones | Chiao-Chun Hsu, Chih-Ming Chen, Sheng-Hsun Lu | 2021-06-29 |
| 10998494 | Perpendicular magnetic random-access memory (MRAM) formation by direct self-assembly method | Chih-Ming Chen, Chern-Yow Hsu, Szu-Yu Wang, Chia-Shiung Tsai, Xiaomeng Chen | 2021-05-04 |
| 10991819 | High electron mobility transistors | Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang | 2021-04-27 |
| 10937878 | Method of implanting dopants into a group III-nitride structure and device formed | Han-Chin Chiu, Chi-Ming Chen, Chen-Hao Chiang | 2021-03-02 |
| 10937900 | Semiconductor structure and manufacturing method thereof | Po-Chun Liu, Chi-Ming Chen, Yao-Chung Chang, Jiun-Lei Jerry Yu, Chen-Hao Chiang | 2021-03-02 |
| 10867792 | High electron mobility transistor (HEMT) having an indium-containing layer and method of manufacturing the same | Po-Chun Liu, Chi-Ming Chen, Min-Chang Ching, Chen-Hao Chiang, Chung-Chieh Hsu | 2020-12-15 |
| 10865103 | Packaging method and associated packaging structure | Chih-Ming Chen, Yuan-Chih Hsieh | 2020-12-15 |
| 10861896 | Capping structure to reduce dark current in image sensors | Po-Chun Liu, Eugene Chen | 2020-12-08 |
| 10833026 | Integrated circuit with backside structures to reduce substrate warp | Chih-Ming Chen, Szu-Yu Wang | 2020-11-10 |
| 10804101 | Semiconductor structure having sets of III-V compound layers and method of forming | Chi-Ming Chen, Po-Chun Liu, Chia-Shiung Tsai | 2020-10-13 |
| 10777649 | Silicon nano-tip thin film for flash memory cells | Tsu-Hui Su, Chih-Ming Chen, Chia-Shiung Tsai, Szu-Yu Wang | 2020-09-15 |
| 10497860 | Perpendicular magnetic random-access memory (MRAM) formation by direct self-assembly method | Chih-Ming Chen, Chern-Yow Hsu, Szu-Yu Wang, Chia-Shiung Tsai, Xiaomeng Chen | 2019-12-03 |
| 10497560 | Uniformity control for Si dot size in flash memory | Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chia-Shiung Tsai, Ru-Liang Lee | 2019-12-03 |
| 10483386 | Semiconductor device, transistor having doped seed layer and method of manufacturing the same | Chi-Ming Chen, Po-Chun Liu, Chia-Shiung Tsai, Ru-Liang Lee | 2019-11-19 |
| 10468486 | SOI substrate, semiconductor device and method for manufacturing the same | Cheng-Ta Wu, Kuo-Hwa Tzeng, Chih-Hao Wang, Yeur-Luen Tu | 2019-11-05 |
| 10351418 | Bond rings in semiconductor devices and methods of forming same | Chih-Ming Chen, Ping-Yin Liu, Yeur-Luen Tu | 2019-07-16 |
| 10294098 | Method for manufacturing a MEMS device by first hybrid bonding a CMOS wafer to a MEMS wafer | Hung-Hua Lin, Chang-Ming Wu, Ping-Yin Liu, Jung-Huei Peng | 2019-05-21 |
| 10276513 | Integrated circuit with backside structures to reduce substrate warp | Chih-Ming Chen, Szu-Yu Wang | 2019-04-30 |
| 10164038 | Method of implanting dopants into a group III-nitride structure and device formed | Han-Chin Chiu, Chen-Hao Chiang, Chi-Ming Chen | 2018-12-25 |
| 10157994 | High electron mobility transistor and method of forming the same | Han-Chin Chiu, Chi-Ming Chen, Chia-Shiung Tsai | 2018-12-18 |
| 10109736 | Superlattice buffer structure for gallium nitride transistors | Chi-Ming Chen, Po-Chun Liu | 2018-10-23 |
| 10109729 | High electron mobility transistors | Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang | 2018-10-23 |
| 10079296 | High electron mobility transistor with indium nitride layer | Chen-Hao Chiang, Po-Chun Liu, Chi-Ming Chen, Min-Chang Ching, Chia-Shiung Tsai +1 more | 2018-09-18 |
| 10074537 | Method of forming semiconductor structure having sets of III-V compound layers | Chi-Ming Chen, Po-Chun Liu, Chia-Shiung Tsai | 2018-09-11 |
| 10014402 | High electron mobility transistor (HEMT) device structure | Kuei-Ming Chen, Chi-Ming Chen | 2018-07-03 |